From: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
Date: Thu, 4 Apr 2019 17:56:58 +0000 (+0200)
Subject: Add m.d.sync return to get_a and get_b cases
X-Git-Tag: ls180-24jan2020~1346
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=733ffe52166d1188c1a1c20995858a1028fdfacb;p=ieee754fpu.git

Add m.d.sync return to get_a and get_b cases
---

diff --git a/src/add/fmul.py b/src/add/fmul.py
index a65700eb..25944a83 100644
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -3,6 +3,7 @@ from nmigen.cli import main, verilog
 
 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPState
 from fpcommon.getop import FPGetOp
+from singlepipe import eq
 
 
 class FPMUL(FPBase):
@@ -15,6 +16,12 @@ class FPMUL(FPBase):
         self.in_b  = FPOp(width)
         self.out_z = FPOp(width)
 
+	self.states = []
+
+    def add_state(self, state):
+	self.states.append(state)
+	return state
+
     def get_fragment(self, platform=None):
         """ creates the HDL code-fragment for FPMUL
         """
@@ -34,19 +41,24 @@ class FPMUL(FPBase):
         m.submodules.b = b
         m.submodules.z = z
 
+        m.d.comb += a.v.eq(self.a.v)
+        m.d.comb += b.v.eq(self.b.v)
+
         with m.FSM() as fsm:
 
             # ******
             # gets operand a
 
             with m.State("get_a"):
-                self.get_op(m, self.in_a, a, "get_b")
+                res = self.get_op(m, self.in_a, a, "get_b")
+		m.d.sync += eq([a, self.in_a.ack], res)
 
             # ******
             # gets operand b
 
             with m.State("get_b"):
-                self.get_op(m, self.in_b, b, "special_cases")
+                res = self.get_op(m, self.in_b, b, "special_cases")
+		m.d.sync += eq([b, self.in_b.ack], res)
 
             # ******
             # special cases