From: lkcl Date: Wed, 25 Aug 2021 15:15:43 +0000 (+0100) Subject: (no commit message) X-Git-Tag: DRAFT_SVP64_0_1~306 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7345e1b258b9a75e340e900d1aac90b91a93a7d0;p=libreriscv.git --- diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn index c9e566ebe..d46bdcab9 100644 --- a/openpower/sv/branches.mdwn +++ b/openpower/sv/branches.mdwn @@ -150,13 +150,11 @@ correspondingly be used instead. If CTR+VLSET Modes are requested, the amount that CTR is decremented by is the value of VL *after* truncation (should that occur). -Note that, interestingly, due to the useful side-effects of `VLSET` mode +Note that, interestingly, due to the side-effects of `VLSET` mode it is actually useful to use Branch Conditional even to perform no actual branch operation, i.e to point to the instruction -after the branch. -If VLSET mode was requested with REMAP, VL will have been set to the -length of one of the loop endpoints, as specified by the bit from -the Branch `BI` field. +after the branch. Truncation of VL would thus conditionally occur yet control +flow alteration would not. Also, the unconditional bit `BO[0]` is still relevant when Predication is applied to the Branch because in `ALL` mode all nonmasked bits have @@ -192,6 +190,11 @@ In addition to the above, it is necessary to select whether, in `svstep` mode, the Vector CR Field is to be overwritten or not: in some cases it is useful to know but in others all that is needed is the branch itself. +*Programming note: One important point is that SVP64 instructions are 64 bit. +(8 bytes not 4). This needs to be taken into consideration when computing +branch offsets: the offset is relative to the start of the instruction, +which includes the SVP64 Prefix* + Pseudocode for Horizontal-First Mode: ```