From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Tue, 11 Aug 2020 08:37:04 +0000 (+0100)
Subject: arch-arm: Fix XN in TLB permissions
X-Git-Tag: v20.1.0.0~312
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=735cf323b513cc9e99452e0c7a231df6d37fb26a;p=gem5.git

arch-arm: Fix XN in TLB permissions

The SIF condition check should be logically ORed with the TLB
entry XN attribute, instead of overriding it.

Change-Id: I70b38d97bbdc82b9f385d40ad06546785fc2c5bb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32635
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index f67475bf3..4d54b54b7 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -833,7 +833,8 @@ TLB::checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode,
     bool w = is_write;
     bool x = is_fetch;
 
-    xn = ArmSystem::haveEL(tc, EL3) && isSecure && te->ns && scr.sif;
+    if (ArmSystem::haveEL(tc, EL3) && isSecure && te->ns && scr.sif)
+        xn = true;
 
     // grant_read is used for faults from an atomic instruction that
     // both reads and writes from a memory location. From a ISS point