From: Iago Toral Quiroga Date: Thu, 1 Sep 2016 12:23:26 +0000 (+0200) Subject: i965/vec4: prevent src/dst hazards during 64-bit register allocation X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=73610384a8357287cef64434c789ff03c2f6f37a;p=mesa.git i965/vec4: prevent src/dst hazards during 64-bit register allocation 8-wide compressed DF operations are executed as two separate 4-wide DF operations. In that scenario, we have to be careful when we allocate register space for their operands to prevent the case where the first half of the instruction overwrites the source of the second half. To do this we mark compressed instructions as having hazards to make sure that ther register allocators assigns a register regions for the destination that does not overlap with the region assigned for any of its source operands. Reviewed-by: Matt Turner --- diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index 951c691390d..a51a3fb8a5d 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp @@ -194,7 +194,13 @@ vec4_instruction::has_source_and_destination_hazard() const case TES_OPCODE_ADD_INDIRECT_URB_OFFSET: return true; default: - return false; + /* 8-wide compressed DF operations are executed as two 4-wide operations, + * so we have a src/dst hazard if the first half of the instruction + * overwrites the source of the second half. Prevent this by marking + * compressed instructions as having src/dst hazards, so the register + * allocator assigns safe register regions for dst and srcs. + */ + return size_written > REG_SIZE; } }