From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 19 May 2021 10:28:25 +0000 (+0100)
Subject: corrections to stf/lf RA_OR_ZERO not in all cases
X-Git-Tag: xlen-bcd~591
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7362886c43f39bcbea15674305462369a172a497;p=openpower-isa.git

corrections to stf/lf RA_OR_ZERO not in all cases
---

diff --git a/openpower/isatables/major.csv b/openpower/isatables/major.csv
index 2c323ae2..45c7446b 100644
--- a/openpower/isatables/major.csv
+++ b/openpower/isatables/major.csv
@@ -13,9 +13,9 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 34,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,1,lbz,D
 35,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,1,0,0,0,NONE,0,1,lbzu,D
 50,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,FRT,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,lfd,D
-51,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,FRT,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,lfdu,D
+51,LDST,OP_LOAD,RA,CONST_SI,NONE,FRT,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,lfdu,D
 48,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,1,0,NONE,0,1,lfs,D
-49,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,1,0,NONE,0,1,lfsu,D
+49,LDST,OP_LOAD,RA,CONST_SI,NONE,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,1,0,NONE,0,1,lfsu,D
 42,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,0,0,0,0,NONE,0,1,lha,D
 43,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,1,0,0,0,NONE,0,1,lhau,D
 40,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,lhz,D
@@ -31,9 +31,9 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 38,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,1,stb,D
 39,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is1B,0,0,1,0,0,0,NONE,0,1,stbu,D
 54,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,FRS,NONE,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,stfd,D
-55,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,FRS,NONE,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,stfdu,D
+55,LDST,OP_STORE,RA,CONST_SI,FRS,NONE,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,stfdu,D
 52,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,FRS,NONE,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,1,0,NONE,0,1,stfs,D
-53,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,FRS,NONE,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,1,0,NONE,0,1,stfsu,D
+53,LDST,OP_STORE,RA,CONST_SI,FRS,NONE,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,1,0,NONE,0,1,stfsu,D
 44,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,sth,D
 45,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,sthu,D
 36,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,stw,D
diff --git a/openpower/isatables/minor_31.csv b/openpower/isatables/minor_31.csv
index df2774cb..0c722fb2 100644
--- a/openpower/isatables/minor_31.csv
+++ b/openpower/isatables/minor_31.csv
@@ -93,11 +93,11 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 0b0000110101,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,ldux,X
 0b0000010101,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,ldx,X
 0b1001010111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,FRT,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,0,lfdx,X
-0b1001110111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,FRT,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,0,lfdux,X
+0b1001110111,LDST,OP_LOAD,RA,RB,NONE,FRT,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,0,lfdux,X
 0b1101010111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,1,0,0,0,0,NONE,0,0,lfiwax,X
 0b1101110111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,0,lfiwzx,X
 0b1000010111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,1,0,NONE,0,0,lfsx,X
-0b1000110111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,1,0,NONE,0,0,lfsux,X
+0b1000110111,LDST,OP_LOAD,RA,RB,NONE,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,1,0,NONE,0,0,lfsux,X
 0b0001110100,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,1,0,0,NONE,0,1,lharx,X
 0b0101110111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,1,0,0,0,NONE,0,1,lhaux,X
 0b0101010111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,0,0,0,0,NONE,0,1,lhax,X
@@ -169,10 +169,10 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 0b0010110101,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,stdux,X
 0b0010010101,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,stdx,X
 0b1011010111,LDST,OP_STORE,RA_OR_ZERO,RB,FRS,NONE,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,0,stfdx,X
-0b1011110111,LDST,OP_STORE,RA_OR_ZERO,RB,FRS,NONE,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,0,stfdux,X
+0b1011110111,LDST,OP_STORE,RA,RB,FRS,NONE,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,0,stfdux,X
 0b1111010111,LDST,OP_STORE,RA_OR_ZERO,RB,FRS,NONE,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,0,stfiwx,X
-0b1010010111,LDST,OP_STORE,RA_OR_ZERO,RB,FRS,NONE,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,1,0,NONE,0,0,stfsx,X
-0b1010110111,LDST,OP_STORE,RA_OR_ZERO,RB,FRS,NONE,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,1,0,NONE,0,0,stfsux,X
+0b1010010111,LDST,OP_STORE,RA,RB,FRS,NONE,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,1,0,NONE,0,0,stfsx,X
+0b1010110111,LDST,OP_STORE,RA,RB,FRS,NONE,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,1,0,NONE,0,0,stfsux,X
 0b1110010110,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is2B,1,0,0,0,0,0,NONE,0,1,sthbrx,X
 0b1110110101,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is2B,0,0,cix,0,0,0,NONE,0,1,sthcix,X
 0b1011010110,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,CR0,0,0,ZERO,0,is2B,0,0,0,1,0,0,ONE,0,1,sthcx,X