From: whitequark <cz@m-labs.hk>
Date: Tue, 11 Jun 2019 03:54:22 +0000 (+0000)
Subject: back.pysim: check for a clock being added twice.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=73631ee6e2bf47d016ff179796e59176b0cbed3e;p=nmigen.git

back.pysim: check for a clock being added twice.

This commit adds a best-effort error for a common mistake of adding
a clock driving the same domain twice, such as a result of
a copy-paste error.

Fixes #27.
---

diff --git a/nmigen/back/pysim.py b/nmigen/back/pysim.py
index 530ee7d..fee545a 100644
--- a/nmigen/back/pysim.py
+++ b/nmigen/back/pysim.py
@@ -366,6 +366,7 @@ class Simulator:
         self._delta           = 0.
         self._epsilon         = 1e-10
         self._fastest_clock   = self._epsilon
+        self._all_clocks      = set()         # {str/domain}
         self._state           = _State()
 
         self._processes       = set()         # {process}
@@ -426,6 +427,9 @@ class Simulator:
     def add_clock(self, period, phase=None, domain="sync"):
         if self._fastest_clock == self._epsilon or period < self._fastest_clock:
             self._fastest_clock = period
+        if domain in self._all_clocks:
+            raise ValueError("Domain '{}' already has a clock driving it"
+                             .format(domain))
 
         half_period = period / 2
         if phase is None:
@@ -440,6 +444,7 @@ class Simulator:
                 yield clk.eq(0)
                 yield Delay(half_period)
         self.add_process(clk_process)
+        self._all_clocks.add(domain)
 
     def __enter__(self):
         if self._vcd_file:
diff --git a/nmigen/test/test_sim.py b/nmigen/test/test_sim.py
index ff3986d..52a1f76 100644
--- a/nmigen/test/test_sim.py
+++ b/nmigen/test/test_sim.py
@@ -388,6 +388,13 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
                         "a generator function"):
                 sim.add_process(1)
 
+    def test_add_clock_wrong(self):
+        with self.assertSimulation(Module()) as sim:
+            sim.add_clock(1)
+            with self.assertRaises(ValueError,
+                    msg="Domain 'sync' already has a clock driving it"):
+                sim.add_clock(1)
+
     def test_eq_signal_unused_wrong(self):
         self.setUp_lhs_rhs()
         self.s = Signal()