From: lkcl <lkcl@web>
Date: Wed, 8 Sep 2021 00:33:46 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~185
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=736be5080bfeff709d3a71fbb154de34db1911a5;p=libreriscv.git

---

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 4167096e1..b4baaf078 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -111,6 +111,10 @@ Rc=1 is a *co-result* accompanying the main arithmetic result, whereas
 for CR-based operations the CR Field or CR bit *is* itself the result
 of the operation.
 
+Therefore, logically, Predicate-result needs to be adapted to
+test the actual result of the CR-based instruction, rather than
+test the co-resultant CR when Rc=1.
+
     for i in range(VL):
         # predication test, skip all masked out elements.
         # skips when sz=0