From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Thu, 4 Apr 2019 14:39:19 +0000 (-0700)
Subject: t:$dff* -> t:$dff t:$dffe
X-Git-Tag: yosys-0.9~171^2~25
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=736e19f02d9980691e244e08b711c5e8c0b4fc76;p=yosys.git

t:$dff* -> t:$dff t:$dffe
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 601a6811d..5a3725e7d 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -113,7 +113,7 @@ struct SynthXilinxPass : public Pass
 		log("        dffsr2dff\n");
 		log("        dff2dffe\n");
 		log("        opt -full\n");
-		log("        simplemap t:$dff* (without -nosrl and without -retime only)\n");
+		log("        simplemap t:$dff t:$dffe (without -nosrl and without -retime only)\n");
 		log("        shregmap -tech xilinx -minlen 3 (without -nosrl and without -retime only)\n");
 		log("        techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n");
 		log("        opt -fast\n");
@@ -266,7 +266,7 @@ struct SynthXilinxPass : public Pass
 			Pass::call(design, "opt -full");
 
 			if (!nosrl && !retime) {
-				Pass::call(design, "simplemap t:$dff*");
+				Pass::call(design, "simplemap t:$dff t:$dffe");
 				Pass::call(design, "shregmap -tech xilinx -minlen 3");
 			}