From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 4 Mar 2021 18:15:40 +0000 (+0000)
Subject: whoops microwatt already allocates SPR 720
X-Git-Tag: convert-csv-opcode-to-binary~120
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=736f836b3284802b73e0c186955f1c8671f697ff;p=soc.git

whoops microwatt already allocates SPR 720
---

diff --git a/libreriscv b/libreriscv
index a89e605a..0863c291 160000
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit a89e605aae22b1f7e26ddcb9577a8271d94d009e
+Subproject commit 0863c2918838890e88ef7d9f2ace66a8476fd3f2
diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 6077aa73..6fa183a8 100644
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -797,14 +797,14 @@ class PowerDecodeSubset(Elaboratable):
         comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
 
         # Microwatt doesn't implement the partition table
-        # instead has PRTBL(SVSRR0) register (SPR) to point to process table
+        # instead has PRTBL register (SPR) to point to process table
         is_spr_mv = Signal()
         is_mmu_spr = Signal()
         comb += is_spr_mv.eq((internal_op == MicrOp.OP_MTSPR) |
                              (internal_op == MicrOp.OP_MFSPR))
         comb += is_mmu_spr.eq((spr == SPR.DSISR.value) |
                               (spr == SPR.DAR.value) |
-                              (spr == SPR.SVSRR0.value) |
+                              (spr == SPR.PRTBL.value) |
                               (spr == SPR.PIDR.value))
         # MMU must receive MMU SPRs
         with m.If(is_spr_mv & (fn == Function.SPR) & is_mmu_spr):