From: Christophe Lyon Date: Wed, 21 Jan 2015 10:11:44 +0000 (+0000) Subject: [ARM/AArch64][testsuite] Add vqdmlal and vqdmlsl tests. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7378039064d2ab688efa47055134a3dc327afc85;p=gcc.git [ARM/AArch64][testsuite] Add vqdmlal and vqdmlsl tests. 2015-01-21 Christophe Lyon * gcc.target/aarch64/advsimd-intrinsics/vqdmlXl.inc: New file. * gcc.target/aarch64/advsimd-intrinsics/vqdmlal.c: New file. * gcc.target/aarch64/advsimd-intrinsics/vqdmlsl.c: New file. From-SVN: r219930 --- diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 006f67c406f..6414a125e62 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2015-01-21 Christophe Lyon + + * gcc.target/aarch64/advsimd-intrinsics/vqdmlXl.inc: New file. + * gcc.target/aarch64/advsimd-intrinsics/vqdmlal.c: New file. + * gcc.target/aarch64/advsimd-intrinsics/vqdmlsl.c: New file. + 2015-01-20 Jeff Law PR target/59946 diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlXl.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlXl.inc new file mode 100644 index 00000000000..cd61fd45707 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlXl.inc @@ -0,0 +1,63 @@ +#define FNNAME1(NAME) exec_ ## NAME +#define FNNAME(NAME) FNNAME1(NAME) + +void FNNAME (INSN_NAME) (void) +{ + /* vector_res = OP(vector, vector3, vector4), + then store the result. */ +#define TEST_VQDMLXL1(INSN, T1, T2, W, W2, N, EXPECTED_CUMULATIVE_SAT, CMT) \ + Set_Neon_Cumulative_Sat(0, VECT_VAR(vector_res, T1, W, N)); \ + VECT_VAR(vector_res, T1, W, N) = \ + INSN##_##T2##W2(VECT_VAR(vector, T1, W, N), \ + VECT_VAR(vector3, T1, W2, N), \ + VECT_VAR(vector4, T1, W2, N)); \ + vst1q_##T2##W(VECT_VAR(result, T1, W, N), \ + VECT_VAR(vector_res, T1, W, N)); \ + CHECK_CUMULATIVE_SAT(TEST_MSG, T1, W, N, EXPECTED_CUMULATIVE_SAT, CMT) + +#define TEST_VQDMLXL(INSN, T1, T2, W, W2, N, EXPECTED_CUMULATIVE_SAT, CMT) \ + TEST_VQDMLXL1(INSN, T1, T2, W, W2, N, EXPECTED_CUMULATIVE_SAT, CMT) + + DECL_VARIABLE(vector, int, 32, 4); + DECL_VARIABLE(vector3, int, 16, 4); + DECL_VARIABLE(vector4, int, 16, 4); + DECL_VARIABLE(vector_res, int, 32, 4); + DECL_VARIABLE(vector, int, 64, 2); + DECL_VARIABLE(vector3, int, 32, 2); + DECL_VARIABLE(vector4, int, 32, 2); + DECL_VARIABLE(vector_res, int, 64, 2); + + clean_results (); + + VLOAD(vector, buffer, q, int, s, 32, 4); + VLOAD(vector, buffer, q, int, s, 64, 2); + + VDUP(vector3, , int, s, 16, 4, 0x55); + VDUP(vector4, , int, s, 16, 4, 0xBB); + VDUP(vector3, , int, s, 32, 2, 0x55); + VDUP(vector4, , int, s, 32, 2, 0xBB); + + TEST_VQDMLXL(INSN_NAME, int, s, 32, 16, 4, expected_cumulative_sat, ""); + TEST_VQDMLXL(INSN_NAME, int, s, 64, 32, 2, expected_cumulative_sat, ""); + + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, ""); + + VDUP(vector3, , int, s, 16, 4, 0x8000); + VDUP(vector4, , int, s, 16, 4, 0x8000); + VDUP(vector3, , int, s, 32, 2, 0x80000000); + VDUP(vector4, , int, s, 32, 2, 0x80000000); + +#define TEST_MSG2 "with saturation" + TEST_VQDMLXL(INSN_NAME, int, s, 32, 16, 4, expected_cumulative_sat2, TEST_MSG2); + TEST_VQDMLXL(INSN_NAME, int, s, 64, 32, 2, expected_cumulative_sat2, TEST_MSG2); + + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected2, TEST_MSG2); + CHECK(TEST_MSG, int, 64, 2, PRIx64, expected2, TEST_MSG2); +} + +int main (void) +{ + FNNAME (INSN_NAME) (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlal.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlal.c new file mode 100644 index 00000000000..c53a90a1a89 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlal.c @@ -0,0 +1,27 @@ +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +#define INSN_NAME vqdmlal +#define TEST_MSG "VQDMLAL" + +/* Expected values of cumulative_saturation flag. */ +int VECT_VAR(expected_cumulative_sat,int,32,4) = 0; +int VECT_VAR(expected_cumulative_sat,int,64,2) = 0; + +/* Expected results. */ +VECT_VAR_DECL(expected,int,32,4) [] = { 0x7c1e, 0x7c1f, 0x7c20, 0x7c21 }; +VECT_VAR_DECL(expected,int,64,2) [] = { 0x7c1e, 0x7c1f }; + +/* Expected values of cumulative_saturation flag when saturation + occurs. */ +int VECT_VAR(expected_cumulative_sat2,int,32,4) = 1; +int VECT_VAR(expected_cumulative_sat2,int,64,2) = 1; + +/* Expected results when saturation occurs. */ +VECT_VAR_DECL(expected2,int,32,4) [] = { 0x7fffffef, 0x7ffffff0, + 0x7ffffff1, 0x7ffffff2 }; +VECT_VAR_DECL(expected2,int,64,2) [] = { 0x7fffffffffffffef, + 0x7ffffffffffffff0 }; + +#include "vqdmlXl.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlsl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlsl.c new file mode 100644 index 00000000000..56e0b61d4a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlsl.c @@ -0,0 +1,29 @@ +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +#define INSN_NAME vqdmlsl +#define TEST_MSG "VQDMLSL" + +/* Expected values of cumulative_saturation flag. */ +int VECT_VAR(expected_cumulative_sat,int,32,4) = 0; +int VECT_VAR(expected_cumulative_sat,int,64,2) = 0; + +/* Expected results. */ +VECT_VAR_DECL(expected,int,32,4) [] = { 0xffff83c2, 0xffff83c3, + 0xffff83c4, 0xffff83c5 }; +VECT_VAR_DECL(expected,int,64,2) [] = { 0xffffffffffff83c2, + 0xffffffffffff83c3 }; + +/* Expected values of cumulative_saturation flag when saturation + occurs. */ +int VECT_VAR(expected_cumulative_sat2,int,32,4) = 1; +int VECT_VAR(expected_cumulative_sat2,int,64,2) = 1; + +/* Expected results when saturation occurs. */ +VECT_VAR_DECL(expected2,int,32,4) [] = { 0x80000000, 0x80000000, + 0x80000000, 0x80000000 }; +VECT_VAR_DECL(expected2,int,64,2) [] = { 0x8000000000000000, + 0x8000000000000000 }; + +#include "vqdmlXl.inc"