From: lkcl <lkcl@web>
Date: Mon, 27 Nov 2023 14:18:14 +0000 (+0000)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=739d73fb4a;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 8fe2d8646..dff204a75 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -141,6 +141,12 @@ every conceivable way.
 when computing branch offsets: the offset is relative to the start of
 the instruction, which **includes** the SVP64 Prefix*
 
+*Programming note: SV Branch-conditional instructions have no destination
+register, only a source (`BI`). Therefore the looping will occur even on
+Scalar BI (`sv.bc/all 16, 0, location`). If this is not desirable behaviour
+and only a single scalar test is required
+use a single-bit unary predicate mask such as `sm=1<<r3`*
+
 ## Format and fields
 
 With element-width overrides being meaningless for Condition Register