From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 9 Apr 2023 09:30:08 +0000 (+0100)
Subject: add postinc reg profiles to optables.csv
X-Git-Tag: opf_rfc_ls012_v1~50
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=73a38dbd74aa313fa071205d1c61d403d93a5ba5;p=libreriscv.git

add postinc reg profiles to optables.csv
---

diff --git a/openpower/sv/rfc/ls012.mdwn b/openpower/sv/rfc/ls012.mdwn
index 68a57e2c8..0bbfa2abd 100644
--- a/openpower/sv/rfc/ls012.mdwn
+++ b/openpower/sv/rfc/ls012.mdwn
@@ -370,7 +370,8 @@ The key to headings and sections are as follows:
 * **XO Cost** - the number of bits required in the XO Field. whilst not
   the full picture it is a good indicator as to how costly in terms
   of Opcode Allocation a given instruction will be.  Lower number is
-  a higher cost for the Power ISA's precious remaining Opcode space
+  a higher cost for the Power ISA's precious remaining Opcode space.
+  "PO" indicates that an entire Primary Opcode is required.
 * **rfc** the Libre-SOC External RFC resource,
   <https://libre-soc.org/openpower/sv/rfc/> where advance notice of
   upcoming RFCs in development may be found.
@@ -389,6 +390,12 @@ The key to headings and sections are as follows:
   (UnVectoriseable),
   EXT3xx, was available in an early Draft RFC but has been made "RESERVED"
   instead.  see [[sv/po9_encoding]].
+* **regs** - a guide to register usage, to how costly Hazard Management
+  will be, in hardware:
+  - 1R: reads one GPR/FPR/SPR/CR.
+  - 1W: writes one GPR/FPR/SPR/CR. 
+  - 1r: reads one CR *Field*.
+  - 1w: writes one CR *Field*
 
 [[!inline pages="openpower/sv/rfc/ls012/areas.mdwn" raw=yes ]]
 [[!inline pages="openpower/sv/rfc/ls012/xo_cost.mdwn" raw=yes ]]
diff --git a/openpower/sv/rfc/ls012/optable.csv b/openpower/sv/rfc/ls012/optable.csv
index e7f096e27..833dd9e98 100644
--- a/openpower/sv/rfc/ls012/optable.csv
+++ b/openpower/sv/rfc/ls012/optable.csv
@@ -1,24 +1,24 @@
 op, rfc, priority, cost, SVP64, group, PO1, page, regs
 # LD/ST-Postincrement (FP TODO)
-lbzup,    ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 1R2W
-lbzupx,   ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 2R2W
-lhzup,    ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 1R2W
-lhzupx,   ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 2R2W
-lhaup,    ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 1R2W
-lhaupx,   ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 2R2W
-lwzup,    ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 1R2W
-lwzupx,   ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 2R2W
-lwaupx,   ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 2R2W
-ldup,     ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 1R2W
-ldupx,    ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 2R2W
-stbup,    ls011, high, ??, yes, EXT2xx, ??, isa/pifixedstore, 2R1W
-stbupx,   ls011, high, ??, yes, EXT2xx, ??, isa/pifixedstore, 3R1W
-sthup,    ls011, high, ??, yes, EXT2xx, ??, isa/pifixedstore, 2R1W
-sthupx,   ls011, high, ??, yes, EXT2xx, ??, isa/pifixedstore, 3R1W
-stwup,    ls011, high, ??, yes, EXT2xx, ??, isa/pifixedstore, 2R1W
-stwupx,   ls011, high, ??, yes, EXT2xx, ??, isa/pifixedstore, 3R1W
-stdup,    ls011, high, ??, yes, EXT2xx, ??, isa/pifixedstore, 2R1W
-stdupx,   ls011, high, ??, yes, EXT2xx, ??, isa/pifixedstore, 3R1W
+lbzup,    ls011, high, PO, yes, EXT2xx, ??, isa/pifixedload, 1R2W
+lbzupx,   ls011, high, 10, yes, EXT2xx, ??, isa/pifixedload, 2R2W
+lhzup,    ls011, high, PO, yes, EXT2xx, ??, isa/pifixedload, 1R2W
+lhzupx,   ls011, high, 10, yes, EXT2xx, ??, isa/pifixedload, 2R2W
+lhaup,    ls011, high, PO, yes, EXT2xx, ??, isa/pifixedload, 1R2W
+lhaupx,   ls011, high, 10, yes, EXT2xx, ??, isa/pifixedload, 2R2W
+lwzup,    ls011, high, PO, yes, EXT2xx, ??, isa/pifixedload, 1R2W
+lwzupx,   ls011, high, 10, yes, EXT2xx, ??, isa/pifixedload, 2R2W
+lwaupx,   ls011, high, 10, yes, EXT2xx, ??, isa/pifixedload, 2R2W
+ldup,     ls011, high, PO, yes, EXT2xx, ??, isa/pifixedload, 1R2W
+ldupx,    ls011, high, 10, yes, EXT2xx, ??, isa/pifixedload, 2R2W
+stbup,    ls011, high, PO, yes, EXT2xx, ??, isa/pifixedstore, 2R1W
+stbupx,   ls011, high, 10, yes, EXT2xx, ??, isa/pifixedstore, 3R1W
+sthup,    ls011, high, PO, yes, EXT2xx, ??, isa/pifixedstore, 2R1W
+sthupx,   ls011, high, 10, yes, EXT2xx, ??, isa/pifixedstore, 3R1W
+stwup,    ls011, high, PO, yes, EXT2xx, ??, isa/pifixedstore, 2R1W
+stwupx,   ls011, high, 10, yes, EXT2xx, ??, isa/pifixedstore, 3R1W
+stdup,    ls011, high, PO, yes, EXT2xx, ??, isa/pifixedstore, 2R1W
+stdupx,   ls011, high, 10, yes, EXT2xx, ??, isa/pifixedstore, 3R1W
 FP-LD,    ls011, high, ??, yes, EXT2xx, ??, TODO,
 FP-ST,    ls011, high, ??, yes, EXT2xx, ??, TODO,
 # Bitmanip LUT2/3 operations. high cost high reward