From: Luke Kenneth Casson Leighton Date: Sun, 18 Apr 2021 10:53:42 +0000 (+0000) Subject: use correct arguments to litex build to create 4k srams sigh X-Git-Tag: LS180_RC3~111 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=73b3dfd82df8183042def7d2d4751d9307deea93;p=soclayout.git use correct arguments to litex build to create 4k srams sigh --- diff --git a/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v b/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v index c9fdc8d..08690af 100644 --- a/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v +++ b/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v @@ -1,7 +1,13 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-04-18 11:23:13 +// Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-04-18 11:51:26 //-------------------------------------------------------------------------------- module ls180( + input wire uart_tx, + input wire uart_rx, + output wire spimaster_clk, + output wire spimaster_mosi, + output wire spimaster_cs_n, + input wire spimaster_miso, input wire [15:0] gpio_i, output wire [15:0] gpio_o, output wire [15:0] gpio_oe, @@ -24,14 +30,11 @@ module ls180( input wire i2c_sda_i, output wire i2c_sda_o, output wire i2c_sda_oe, - output wire spimaster_clk, - output wire spimaster_mosi, - output wire spimaster_cs_n, - input wire spimaster_miso, - input wire uart_tx, - input wire uart_rx, input wire sys_clk, input wire sys_rst, + input wire [1:0] sys_clksel_i, + output wire sys_pll_18_o, + output wire sys_pll_lck_o, input wire jtag_tms, input wire jtag_tck, input wire jtag_tdi, @@ -101,6 +104,50 @@ wire libresocsim_libresoc_jtag_wb_we; reg [2:0] libresocsim_libresoc_jtag_wb_cti = 3'd0; reg [1:0] libresocsim_libresoc_jtag_wb_bte = 2'd0; wire libresocsim_libresoc_jtag_wb_err; +reg [28:0] libresocsim_libresoc_interface0_adr = 29'd0; +reg [63:0] libresocsim_libresoc_interface0_dat_w = 64'd0; +wire [63:0] libresocsim_libresoc_interface0_dat_r; +reg [7:0] libresocsim_libresoc_interface0_sel = 8'd0; +wire libresocsim_libresoc_interface0_cyc; +wire libresocsim_libresoc_interface0_stb; +wire libresocsim_libresoc_interface0_ack; +wire libresocsim_libresoc_interface0_we; +wire [2:0] libresocsim_libresoc_interface0_cti; +wire [1:0] libresocsim_libresoc_interface0_bte; +wire libresocsim_libresoc_interface0_err; +reg [28:0] libresocsim_libresoc_interface1_adr = 29'd0; +reg [63:0] libresocsim_libresoc_interface1_dat_w = 64'd0; +wire [63:0] libresocsim_libresoc_interface1_dat_r; +reg [7:0] libresocsim_libresoc_interface1_sel = 8'd0; +wire libresocsim_libresoc_interface1_cyc; +wire libresocsim_libresoc_interface1_stb; +wire libresocsim_libresoc_interface1_ack; +wire libresocsim_libresoc_interface1_we; +wire [2:0] libresocsim_libresoc_interface1_cti; +wire [1:0] libresocsim_libresoc_interface1_bte; +wire libresocsim_libresoc_interface1_err; +reg [28:0] libresocsim_libresoc_interface2_adr = 29'd0; +reg [63:0] libresocsim_libresoc_interface2_dat_w = 64'd0; +wire [63:0] libresocsim_libresoc_interface2_dat_r; +reg [7:0] libresocsim_libresoc_interface2_sel = 8'd0; +wire libresocsim_libresoc_interface2_cyc; +wire libresocsim_libresoc_interface2_stb; +wire libresocsim_libresoc_interface2_ack; +wire libresocsim_libresoc_interface2_we; +wire [2:0] libresocsim_libresoc_interface2_cti; +wire [1:0] libresocsim_libresoc_interface2_bte; +wire libresocsim_libresoc_interface2_err; +reg [28:0] libresocsim_libresoc_interface3_adr = 29'd0; +reg [63:0] libresocsim_libresoc_interface3_dat_w = 64'd0; +wire [63:0] libresocsim_libresoc_interface3_dat_r; +reg [7:0] libresocsim_libresoc_interface3_sel = 8'd0; +wire libresocsim_libresoc_interface3_cyc; +wire libresocsim_libresoc_interface3_stb; +wire libresocsim_libresoc_interface3_ack; +wire libresocsim_libresoc_interface3_we; +wire [2:0] libresocsim_libresoc_interface3_cti; +wire [1:0] libresocsim_libresoc_interface3_bte; +wire libresocsim_libresoc_interface3_err; wire libresocsim_libresoc_jtag_tck; wire libresocsim_libresoc_jtag_tms; wire libresocsim_libresoc_jtag_tdi; @@ -109,6 +156,15 @@ reg [63:0] libresocsim_libresoc0 = 64'd0; wire libresocsim_libresoc1; wire libresocsim_libresoc2; wire [63:0] libresocsim_libresoc3; +wire libresocsim_libresoc_pll_18_o; +wire [1:0] libresocsim_libresoc_clk_sel; +wire libresocsim_libresoc_pll_lck_o; +reg libresocsim_libresoc_constraintmanager_uart_tx = 1'd1; +reg libresocsim_libresoc_constraintmanager_uart_rx = 1'd0; +reg libresocsim_libresoc_constraintmanager_spimaster_clk = 1'd0; +reg libresocsim_libresoc_constraintmanager_spimaster_mosi = 1'd0; +reg libresocsim_libresoc_constraintmanager_spimaster_cs_n = 1'd0; +wire libresocsim_libresoc_constraintmanager_spimaster_miso; wire [15:0] libresocsim_libresoc_constraintmanager_gpio_i; reg [15:0] libresocsim_libresoc_constraintmanager_gpio_o = 16'd0; reg [15:0] libresocsim_libresoc_constraintmanager_gpio_oe = 16'd0; @@ -131,12 +187,6 @@ wire libresocsim_libresoc_constraintmanager_i2c_scl; wire libresocsim_libresoc_constraintmanager_i2c_sda_i; wire libresocsim_libresoc_constraintmanager_i2c_sda_o; wire libresocsim_libresoc_constraintmanager_i2c_sda_oe; -reg libresocsim_libresoc_constraintmanager_spimaster_clk = 1'd0; -reg libresocsim_libresoc_constraintmanager_spimaster_mosi = 1'd0; -reg libresocsim_libresoc_constraintmanager_spimaster_cs_n = 1'd0; -wire libresocsim_libresoc_constraintmanager_spimaster_miso; -reg libresocsim_libresoc_constraintmanager_uart_tx = 1'd1; -reg libresocsim_libresoc_constraintmanager_uart_rx = 1'd0; reg [29:0] libresocsim_interface0_converted_interface_adr = 30'd0; reg [31:0] libresocsim_interface0_converted_interface_dat_w = 32'd0; wire [31:0] libresocsim_interface0_converted_interface_dat_r; @@ -178,7 +228,7 @@ wire libresocsim_ram_bus_we; wire [2:0] libresocsim_ram_bus_cti; wire [1:0] libresocsim_ram_bus_bte; reg libresocsim_ram_bus_err = 1'd0; -wire [6:0] libresocsim_adr; +wire [4:0] libresocsim_adr; wire [31:0] libresocsim_dat_r; reg [3:0] libresocsim_we = 4'd0; wire [31:0] libresocsim_dat_w; @@ -224,6 +274,50 @@ wire [4:0] ram_adr; wire [31:0] ram_dat_r; reg [3:0] ram_we = 4'd0; wire [31:0] ram_dat_w; +wire [29:0] interface0_converted_interface_adr; +wire [31:0] interface0_converted_interface_dat_w; +reg [31:0] interface0_converted_interface_dat_r = 32'd0; +wire [3:0] interface0_converted_interface_sel; +wire interface0_converted_interface_cyc; +wire interface0_converted_interface_stb; +wire interface0_converted_interface_ack; +wire interface0_converted_interface_we; +wire [2:0] interface0_converted_interface_cti; +wire [1:0] interface0_converted_interface_bte; +wire interface0_converted_interface_err; +wire [29:0] interface1_converted_interface_adr; +wire [31:0] interface1_converted_interface_dat_w; +reg [31:0] interface1_converted_interface_dat_r = 32'd0; +wire [3:0] interface1_converted_interface_sel; +wire interface1_converted_interface_cyc; +wire interface1_converted_interface_stb; +wire interface1_converted_interface_ack; +wire interface1_converted_interface_we; +wire [2:0] interface1_converted_interface_cti; +wire [1:0] interface1_converted_interface_bte; +wire interface1_converted_interface_err; +wire [29:0] interface2_converted_interface_adr; +wire [31:0] interface2_converted_interface_dat_w; +reg [31:0] interface2_converted_interface_dat_r = 32'd0; +wire [3:0] interface2_converted_interface_sel; +wire interface2_converted_interface_cyc; +wire interface2_converted_interface_stb; +wire interface2_converted_interface_ack; +wire interface2_converted_interface_we; +wire [2:0] interface2_converted_interface_cti; +wire [1:0] interface2_converted_interface_bte; +wire interface2_converted_interface_err; +wire [29:0] interface3_converted_interface_adr; +wire [31:0] interface3_converted_interface_dat_w; +reg [31:0] interface3_converted_interface_dat_r = 32'd0; +wire [3:0] interface3_converted_interface_sel; +wire interface3_converted_interface_cyc; +wire interface3_converted_interface_stb; +wire interface3_converted_interface_ack; +wire interface3_converted_interface_we; +wire [2:0] interface3_converted_interface_cti; +wire [1:0] interface3_converted_interface_bte; +wire interface3_converted_interface_err; wire sys_clk_1; wire sys_rst_1; wire por_clk; @@ -1060,8 +1154,8 @@ wire [1:0] libresocsim_shared_bte; wire libresocsim_shared_err; wire [2:0] libresocsim_request; reg [1:0] libresocsim_grant = 2'd0; -reg [5:0] libresocsim_slave_sel = 6'd0; -reg [5:0] libresocsim_slave_sel_r = 6'd0; +reg [9:0] libresocsim_slave_sel = 10'd0; +reg [9:0] libresocsim_slave_sel_r = 10'd0; reg libresocsim_error = 1'd0; wire libresocsim_wait; wire libresocsim_done; @@ -1486,6 +1580,9 @@ wire sdrio_clk_117; wire sdrio_clk_118; assign libresocsim_libresoc_reset = libresocsim_reset; +assign libresocsim_libresoc_clk_sel = sys_clksel_i; +assign sys_pll_18_o = libresocsim_libresoc_pll_18_o; +assign sys_pll_lck_o = libresocsim_libresoc_pll_lck_o; always @(*) begin eint_tmp <= 3'd0; eint_tmp[0] <= libresocsim_libresoc_constraintmanager_eint_0; @@ -1520,16 +1617,16 @@ always @(*) begin end assign libresocsim_libresoc_ibus_dat_r = {libresocsim_interface0_converted_interface_dat_r, libresocsim_converter0_dat_r[63:32]}; always @(*) begin - libresocsim_interface0_converted_interface_sel <= 4'd0; libresocsim_interface0_converted_interface_cyc <= 1'd0; - libresocsim_libresoc_ibus_ack <= 1'd0; libresocsim_interface0_converted_interface_stb <= 1'd0; - subfragments_converter0_next_state <= 1'd0; - libresocsim_converter0_counter_subfragments_converter0_next_value <= 1'd0; + libresocsim_libresoc_ibus_ack <= 1'd0; libresocsim_interface0_converted_interface_we <= 1'd0; - libresocsim_converter0_counter_subfragments_converter0_next_value_ce <= 1'd0; + libresocsim_converter0_counter_subfragments_converter0_next_value <= 1'd0; libresocsim_converter0_skip <= 1'd0; + subfragments_converter0_next_state <= 1'd0; libresocsim_interface0_converted_interface_adr <= 30'd0; + libresocsim_converter0_counter_subfragments_converter0_next_value_ce <= 1'd0; + libresocsim_interface0_converted_interface_sel <= 4'd0; subfragments_converter0_next_state <= subfragments_converter0_state; case (subfragments_converter0_state) 1'd1: begin @@ -1580,16 +1677,16 @@ always @(*) begin end assign libresocsim_libresoc_dbus_dat_r = {libresocsim_interface1_converted_interface_dat_r, libresocsim_converter1_dat_r[63:32]}; always @(*) begin - libresocsim_interface1_converted_interface_we <= 1'd0; - subfragments_converter1_next_state <= 1'd0; - libresocsim_converter1_counter_subfragments_converter1_next_value <= 1'd0; - libresocsim_converter1_counter_subfragments_converter1_next_value_ce <= 1'd0; libresocsim_converter1_skip <= 1'd0; libresocsim_libresoc_dbus_ack <= 1'd0; libresocsim_interface1_converted_interface_adr <= 30'd0; + subfragments_converter1_next_state <= 1'd0; + libresocsim_converter1_counter_subfragments_converter1_next_value <= 1'd0; libresocsim_interface1_converted_interface_sel <= 4'd0; + libresocsim_converter1_counter_subfragments_converter1_next_value_ce <= 1'd0; libresocsim_interface1_converted_interface_cyc <= 1'd0; libresocsim_interface1_converted_interface_stb <= 1'd0; + libresocsim_interface1_converted_interface_we <= 1'd0; subfragments_converter1_next_state <= subfragments_converter1_state; case (subfragments_converter1_state) 1'd1: begin @@ -1626,6 +1723,114 @@ always @(*) begin end endcase end +assign libresocsim_libresoc_interface0_cyc = interface0_converted_interface_cyc; +assign libresocsim_libresoc_interface0_stb = interface0_converted_interface_stb; +assign interface0_converted_interface_ack = libresocsim_libresoc_interface0_ack; +assign libresocsim_libresoc_interface0_we = interface0_converted_interface_we; +assign libresocsim_libresoc_interface0_cti = interface0_converted_interface_cti; +assign libresocsim_libresoc_interface0_bte = interface0_converted_interface_bte; +assign interface0_converted_interface_err = libresocsim_libresoc_interface0_err; +always @(*) begin + libresocsim_libresoc_interface0_adr <= 29'd0; + libresocsim_libresoc_interface0_dat_w <= 64'd0; + libresocsim_libresoc_interface0_sel <= 8'd0; + interface0_converted_interface_dat_r <= 32'd0; + case (interface0_converted_interface_adr[0]) + 1'd0: begin + libresocsim_libresoc_interface0_adr <= interface0_converted_interface_adr[29:1]; + libresocsim_libresoc_interface0_sel[3:0] <= 4'd15; + libresocsim_libresoc_interface0_dat_w[31:0] <= interface0_converted_interface_dat_w; + interface0_converted_interface_dat_r <= libresocsim_libresoc_interface0_dat_r[31:0]; + end + 1'd1: begin + libresocsim_libresoc_interface0_adr <= interface0_converted_interface_adr[29:1]; + libresocsim_libresoc_interface0_sel[7:4] <= 4'd15; + libresocsim_libresoc_interface0_dat_w[63:32] <= interface0_converted_interface_dat_w; + interface0_converted_interface_dat_r <= libresocsim_libresoc_interface0_dat_r[63:32]; + end + endcase +end +assign libresocsim_libresoc_interface1_cyc = interface1_converted_interface_cyc; +assign libresocsim_libresoc_interface1_stb = interface1_converted_interface_stb; +assign interface1_converted_interface_ack = libresocsim_libresoc_interface1_ack; +assign libresocsim_libresoc_interface1_we = interface1_converted_interface_we; +assign libresocsim_libresoc_interface1_cti = interface1_converted_interface_cti; +assign libresocsim_libresoc_interface1_bte = interface1_converted_interface_bte; +assign interface1_converted_interface_err = libresocsim_libresoc_interface1_err; +always @(*) begin + libresocsim_libresoc_interface1_dat_w <= 64'd0; + libresocsim_libresoc_interface1_sel <= 8'd0; + interface1_converted_interface_dat_r <= 32'd0; + libresocsim_libresoc_interface1_adr <= 29'd0; + case (interface1_converted_interface_adr[0]) + 1'd0: begin + libresocsim_libresoc_interface1_adr <= interface1_converted_interface_adr[29:1]; + libresocsim_libresoc_interface1_sel[3:0] <= 4'd15; + libresocsim_libresoc_interface1_dat_w[31:0] <= interface1_converted_interface_dat_w; + interface1_converted_interface_dat_r <= libresocsim_libresoc_interface1_dat_r[31:0]; + end + 1'd1: begin + libresocsim_libresoc_interface1_adr <= interface1_converted_interface_adr[29:1]; + libresocsim_libresoc_interface1_sel[7:4] <= 4'd15; + libresocsim_libresoc_interface1_dat_w[63:32] <= interface1_converted_interface_dat_w; + interface1_converted_interface_dat_r <= libresocsim_libresoc_interface1_dat_r[63:32]; + end + endcase +end +assign libresocsim_libresoc_interface2_cyc = interface2_converted_interface_cyc; +assign libresocsim_libresoc_interface2_stb = interface2_converted_interface_stb; +assign interface2_converted_interface_ack = libresocsim_libresoc_interface2_ack; +assign libresocsim_libresoc_interface2_we = interface2_converted_interface_we; +assign libresocsim_libresoc_interface2_cti = interface2_converted_interface_cti; +assign libresocsim_libresoc_interface2_bte = interface2_converted_interface_bte; +assign interface2_converted_interface_err = libresocsim_libresoc_interface2_err; +always @(*) begin + interface2_converted_interface_dat_r <= 32'd0; + libresocsim_libresoc_interface2_sel <= 8'd0; + libresocsim_libresoc_interface2_adr <= 29'd0; + libresocsim_libresoc_interface2_dat_w <= 64'd0; + case (interface2_converted_interface_adr[0]) + 1'd0: begin + libresocsim_libresoc_interface2_adr <= interface2_converted_interface_adr[29:1]; + libresocsim_libresoc_interface2_sel[3:0] <= 4'd15; + libresocsim_libresoc_interface2_dat_w[31:0] <= interface2_converted_interface_dat_w; + interface2_converted_interface_dat_r <= libresocsim_libresoc_interface2_dat_r[31:0]; + end + 1'd1: begin + libresocsim_libresoc_interface2_adr <= interface2_converted_interface_adr[29:1]; + libresocsim_libresoc_interface2_sel[7:4] <= 4'd15; + libresocsim_libresoc_interface2_dat_w[63:32] <= interface2_converted_interface_dat_w; + interface2_converted_interface_dat_r <= libresocsim_libresoc_interface2_dat_r[63:32]; + end + endcase +end +assign libresocsim_libresoc_interface3_cyc = interface3_converted_interface_cyc; +assign libresocsim_libresoc_interface3_stb = interface3_converted_interface_stb; +assign interface3_converted_interface_ack = libresocsim_libresoc_interface3_ack; +assign libresocsim_libresoc_interface3_we = interface3_converted_interface_we; +assign libresocsim_libresoc_interface3_cti = interface3_converted_interface_cti; +assign libresocsim_libresoc_interface3_bte = interface3_converted_interface_bte; +assign interface3_converted_interface_err = libresocsim_libresoc_interface3_err; +always @(*) begin + libresocsim_libresoc_interface3_sel <= 8'd0; + libresocsim_libresoc_interface3_adr <= 29'd0; + interface3_converted_interface_dat_r <= 32'd0; + libresocsim_libresoc_interface3_dat_w <= 64'd0; + case (interface3_converted_interface_adr[0]) + 1'd0: begin + libresocsim_libresoc_interface3_adr <= interface3_converted_interface_adr[29:1]; + libresocsim_libresoc_interface3_sel[3:0] <= 4'd15; + libresocsim_libresoc_interface3_dat_w[31:0] <= interface3_converted_interface_dat_w; + interface3_converted_interface_dat_r <= libresocsim_libresoc_interface3_dat_r[31:0]; + end + 1'd1: begin + libresocsim_libresoc_interface3_adr <= interface3_converted_interface_adr[29:1]; + libresocsim_libresoc_interface3_sel[7:4] <= 4'd15; + libresocsim_libresoc_interface3_dat_w[63:32] <= interface3_converted_interface_dat_w; + interface3_converted_interface_dat_r <= libresocsim_libresoc_interface3_dat_r[63:32]; + end + endcase +end assign libresocsim_reset = libresocsim_reset_re; assign libresocsim_bus_errors_status = libresocsim_bus_errors; always @(*) begin @@ -1635,7 +1840,7 @@ always @(*) begin libresocsim_we[2] <= (((libresocsim_ram_bus_cyc & libresocsim_ram_bus_stb) & libresocsim_ram_bus_we) & libresocsim_ram_bus_sel[2]); libresocsim_we[3] <= (((libresocsim_ram_bus_cyc & libresocsim_ram_bus_stb) & libresocsim_ram_bus_we) & libresocsim_ram_bus_sel[3]); end -assign libresocsim_adr = libresocsim_ram_bus_adr[6:0]; +assign libresocsim_adr = libresocsim_ram_bus_adr[4:0]; assign libresocsim_ram_bus_dat_r = libresocsim_dat_r; assign libresocsim_dat_w = libresocsim_ram_bus_dat_w; assign libresocsim_zero_trigger = (libresocsim_value != 1'd0); @@ -1695,24 +1900,24 @@ assign sdram_slave_p0_rddata_en = sdram_dfi_p0_rddata_en; assign sdram_dfi_p0_rddata = sdram_slave_p0_rddata; assign sdram_dfi_p0_rddata_valid = sdram_slave_p0_rddata_valid; always @(*) begin - sdram_master_p0_ras_n <= 1'd1; - sdram_master_p0_we_n <= 1'd1; - sdram_master_p0_cke <= 1'd0; - sdram_master_p0_odt <= 1'd0; - sdram_master_p0_reset_n <= 1'd0; - sdram_master_p0_act_n <= 1'd1; - sdram_inti_p0_rddata <= 16'd0; - sdram_master_p0_wrdata <= 16'd0; - sdram_inti_p0_rddata_valid <= 1'd0; - sdram_master_p0_wrdata_en <= 1'd0; sdram_master_p0_wrdata_mask <= 2'd0; sdram_master_p0_rddata_en <= 1'd0; + sdram_master_p0_act_n <= 1'd1; + sdram_master_p0_wrdata <= 16'd0; sdram_slave_p0_rddata <= 16'd0; sdram_slave_p0_rddata_valid <= 1'd0; sdram_master_p0_address <= 13'd0; sdram_master_p0_bank <= 2'd0; sdram_master_p0_cas_n <= 1'd1; sdram_master_p0_cs_n <= 1'd1; + sdram_master_p0_ras_n <= 1'd1; + sdram_master_p0_we_n <= 1'd1; + sdram_master_p0_cke <= 1'd0; + sdram_master_p0_odt <= 1'd0; + sdram_master_p0_reset_n <= 1'd0; + sdram_inti_p0_rddata <= 16'd0; + sdram_inti_p0_rddata_valid <= 1'd0; + sdram_master_p0_wrdata_en <= 1'd0; if (sdram_sel) begin sdram_master_p0_address <= sdram_slave_p0_address; sdram_master_p0_bank <= sdram_slave_p0_bank; @@ -1906,6 +2111,11 @@ assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (sdram_bankm assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (sdram_bankmachine0_cmd_buffer_lookahead_level != 1'd0); assign sdram_bankmachine0_cmd_buffer_sink_ready = ((~sdram_bankmachine0_cmd_buffer_source_valid) | sdram_bankmachine0_cmd_buffer_source_ready); always @(*) begin + sdram_bankmachine0_refresh_gnt <= 1'd0; + subfragments_bankmachine0_next_state <= 3'd0; + sdram_bankmachine0_cmd_valid <= 1'd0; + sdram_bankmachine0_row_open <= 1'd0; + sdram_bankmachine0_row_close <= 1'd0; sdram_bankmachine0_cmd_payload_cas <= 1'd0; sdram_bankmachine0_cmd_payload_ras <= 1'd0; sdram_bankmachine0_cmd_payload_we <= 1'd0; @@ -1915,11 +2125,6 @@ always @(*) begin sdram_bankmachine0_cmd_payload_is_write <= 1'd0; sdram_bankmachine0_req_wdata_ready <= 1'd0; sdram_bankmachine0_req_rdata_valid <= 1'd0; - sdram_bankmachine0_refresh_gnt <= 1'd0; - subfragments_bankmachine0_next_state <= 3'd0; - sdram_bankmachine0_cmd_valid <= 1'd0; - sdram_bankmachine0_row_open <= 1'd0; - sdram_bankmachine0_row_close <= 1'd0; subfragments_bankmachine0_next_state <= subfragments_bankmachine0_state; case (subfragments_bankmachine0_state) 1'd1: begin @@ -2063,20 +2268,20 @@ assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (sdram_bankm assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (sdram_bankmachine1_cmd_buffer_lookahead_level != 1'd0); assign sdram_bankmachine1_cmd_buffer_sink_ready = ((~sdram_bankmachine1_cmd_buffer_source_valid) | sdram_bankmachine1_cmd_buffer_source_ready); always @(*) begin + sdram_bankmachine1_cmd_payload_is_read <= 1'd0; + sdram_bankmachine1_cmd_payload_is_write <= 1'd0; + sdram_bankmachine1_req_wdata_ready <= 1'd0; + sdram_bankmachine1_req_rdata_valid <= 1'd0; + sdram_bankmachine1_refresh_gnt <= 1'd0; + sdram_bankmachine1_cmd_valid <= 1'd0; + sdram_bankmachine1_row_col_n_addr_sel <= 1'd0; sdram_bankmachine1_row_open <= 1'd0; sdram_bankmachine1_row_close <= 1'd0; sdram_bankmachine1_cmd_payload_cas <= 1'd0; sdram_bankmachine1_cmd_payload_ras <= 1'd0; sdram_bankmachine1_cmd_payload_we <= 1'd0; - sdram_bankmachine1_row_col_n_addr_sel <= 1'd0; sdram_bankmachine1_cmd_payload_is_cmd <= 1'd0; subfragments_bankmachine1_next_state <= 3'd0; - sdram_bankmachine1_cmd_payload_is_read <= 1'd0; - sdram_bankmachine1_cmd_payload_is_write <= 1'd0; - sdram_bankmachine1_req_wdata_ready <= 1'd0; - sdram_bankmachine1_req_rdata_valid <= 1'd0; - sdram_bankmachine1_refresh_gnt <= 1'd0; - sdram_bankmachine1_cmd_valid <= 1'd0; subfragments_bankmachine1_next_state <= subfragments_bankmachine1_state; case (subfragments_bankmachine1_state) 1'd1: begin @@ -2220,11 +2425,6 @@ assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (sdram_bankm assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (sdram_bankmachine2_cmd_buffer_lookahead_level != 1'd0); assign sdram_bankmachine2_cmd_buffer_sink_ready = ((~sdram_bankmachine2_cmd_buffer_source_valid) | sdram_bankmachine2_cmd_buffer_source_ready); always @(*) begin - sdram_bankmachine2_refresh_gnt <= 1'd0; - sdram_bankmachine2_cmd_valid <= 1'd0; - subfragments_bankmachine2_next_state <= 3'd0; - sdram_bankmachine2_row_open <= 1'd0; - sdram_bankmachine2_row_close <= 1'd0; sdram_bankmachine2_cmd_payload_cas <= 1'd0; sdram_bankmachine2_cmd_payload_ras <= 1'd0; sdram_bankmachine2_cmd_payload_we <= 1'd0; @@ -2234,6 +2434,11 @@ always @(*) begin sdram_bankmachine2_cmd_payload_is_write <= 1'd0; sdram_bankmachine2_req_wdata_ready <= 1'd0; sdram_bankmachine2_req_rdata_valid <= 1'd0; + sdram_bankmachine2_refresh_gnt <= 1'd0; + sdram_bankmachine2_row_open <= 1'd0; + sdram_bankmachine2_cmd_valid <= 1'd0; + subfragments_bankmachine2_next_state <= 3'd0; + sdram_bankmachine2_row_close <= 1'd0; subfragments_bankmachine2_next_state <= subfragments_bankmachine2_state; case (subfragments_bankmachine2_state) 1'd1: begin @@ -2377,6 +2582,13 @@ assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (sdram_bankm assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (sdram_bankmachine3_cmd_buffer_lookahead_level != 1'd0); assign sdram_bankmachine3_cmd_buffer_sink_ready = ((~sdram_bankmachine3_cmd_buffer_source_valid) | sdram_bankmachine3_cmd_buffer_source_ready); always @(*) begin + sdram_bankmachine3_row_open <= 1'd0; + sdram_bankmachine3_row_close <= 1'd0; + sdram_bankmachine3_cmd_payload_cas <= 1'd0; + sdram_bankmachine3_cmd_payload_ras <= 1'd0; + sdram_bankmachine3_cmd_payload_we <= 1'd0; + sdram_bankmachine3_row_col_n_addr_sel <= 1'd0; + sdram_bankmachine3_cmd_payload_is_cmd <= 1'd0; sdram_bankmachine3_cmd_payload_is_read <= 1'd0; sdram_bankmachine3_cmd_payload_is_write <= 1'd0; sdram_bankmachine3_req_wdata_ready <= 1'd0; @@ -2384,13 +2596,6 @@ always @(*) begin subfragments_bankmachine3_next_state <= 3'd0; sdram_bankmachine3_refresh_gnt <= 1'd0; sdram_bankmachine3_cmd_valid <= 1'd0; - sdram_bankmachine3_row_open <= 1'd0; - sdram_bankmachine3_row_close <= 1'd0; - sdram_bankmachine3_cmd_payload_cas <= 1'd0; - sdram_bankmachine3_row_col_n_addr_sel <= 1'd0; - sdram_bankmachine3_cmd_payload_ras <= 1'd0; - sdram_bankmachine3_cmd_payload_we <= 1'd0; - sdram_bankmachine3_cmd_payload_is_cmd <= 1'd0; subfragments_bankmachine3_next_state <= subfragments_bankmachine3_state; case (subfragments_bankmachine3_state) 1'd1: begin @@ -2595,15 +2800,15 @@ assign sdram_dfi_p0_reset_n = 1'd1; assign sdram_dfi_p0_cke = {1{sdram_steerer0}}; assign sdram_dfi_p0_odt = {1{sdram_steerer1}}; always @(*) begin + sdram_en0 <= 1'd0; + sdram_choose_req_want_writes <= 1'd0; subfragments_multiplexer_next_state <= 3'd0; sdram_en1 <= 1'd0; sdram_choose_req_want_reads <= 1'd0; - sdram_choose_req_want_writes <= 1'd0; + sdram_choose_req_cmd_ready <= 1'd0; sdram_cmd_ready <= 1'd0; sdram_choose_req_want_activates <= 1'd0; sdram_steerer_sel <= 2'd0; - sdram_choose_req_cmd_ready <= 1'd0; - sdram_en0 <= 1'd0; sdram_choose_req_want_activates <= sdram_ras_allowed; subfragments_multiplexer_next_state <= subfragments_multiplexer_state; case (subfragments_multiplexer_state) @@ -2723,16 +2928,16 @@ always @(*) begin end assign wb_sdram_dat_r = {litedram_wb_dat_r, converter_dat_r[31:16]}; always @(*) begin + converter_skip <= 1'd0; + wb_sdram_ack <= 1'd0; + litedram_wb_we <= 1'd0; + litedram_wb_adr <= 30'd0; litedram_wb_sel <= 2'd0; litedram_wb_cyc <= 1'd0; litedram_wb_stb <= 1'd0; subfragments_next_state <= 1'd0; converter_counter_subfragments_next_value <= 1'd0; - litedram_wb_we <= 1'd0; converter_counter_subfragments_next_value_ce <= 1'd0; - converter_skip <= 1'd0; - wb_sdram_ack <= 1'd0; - litedram_wb_adr <= 30'd0; subfragments_next_state <= subfragments_state; case (subfragments_state) 1'd1: begin @@ -2963,15 +3168,15 @@ assign libresocsim_libresoc_constraintmanager_i2c_sda_oe = i2c_oe; assign libresocsim_libresoc_constraintmanager_i2c_sda_o = i2c_sda0; assign i2c_sda1 = libresocsim_libresoc_constraintmanager_i2c_sda_i; always @(*) begin + libresocsim_libresocsim_wishbone_dat_r <= 32'd0; libresocsim_next_state <= 2'd0; libresocsim_libresocsim_dat_w_libresocsim_next_value0 <= 8'd0; + libresocsim_libresocsim_wishbone_ack <= 1'd0; libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 <= 1'd0; libresocsim_libresocsim_adr_libresocsim_next_value1 <= 13'd0; libresocsim_libresocsim_adr_libresocsim_next_value_ce1 <= 1'd0; - libresocsim_libresocsim_wishbone_dat_r <= 32'd0; libresocsim_libresocsim_we_libresocsim_next_value2 <= 1'd0; libresocsim_libresocsim_we_libresocsim_next_value_ce2 <= 1'd0; - libresocsim_libresocsim_wishbone_ack <= 1'd0; libresocsim_next_state <= libresocsim_state; case (libresocsim_state) 1'd1: begin @@ -3018,13 +3223,17 @@ assign libresocsim_interface1_converted_interface_err = (libresocsim_shared_err assign libresocsim_libresoc_jtag_wb_err = (libresocsim_shared_err & (libresocsim_grant == 2'd2)); assign libresocsim_request = {libresocsim_libresoc_jtag_wb_cyc, libresocsim_interface1_converted_interface_cyc, libresocsim_interface0_converted_interface_cyc}; always @(*) begin - libresocsim_slave_sel <= 6'd0; - libresocsim_slave_sel[0] <= (libresocsim_shared_adr[29:7] == 1'd0); + libresocsim_slave_sel <= 10'd0; + libresocsim_slave_sel[0] <= (libresocsim_shared_adr[29:5] == 1'd0); libresocsim_slave_sel[1] <= (libresocsim_shared_adr[29:5] == 4'd14); libresocsim_slave_sel[2] <= (libresocsim_shared_adr[29:3] == 27'd100665344); libresocsim_slave_sel[3] <= (libresocsim_shared_adr[29:10] == 20'd786449); - libresocsim_slave_sel[4] <= (libresocsim_shared_adr[29:23] == 7'd72); - libresocsim_slave_sel[5] <= (libresocsim_shared_adr[29:13] == 17'd98304); + libresocsim_slave_sel[4] <= (libresocsim_shared_adr[29:10] == 1'd1); + libresocsim_slave_sel[5] <= (libresocsim_shared_adr[29:10] == 2'd2); + libresocsim_slave_sel[6] <= (libresocsim_shared_adr[29:10] == 2'd3); + libresocsim_slave_sel[7] <= (libresocsim_shared_adr[29:10] == 3'd4); + libresocsim_slave_sel[8] <= (libresocsim_shared_adr[29:23] == 7'd72); + libresocsim_slave_sel[9] <= (libresocsim_shared_adr[29:13] == 17'd98304); end assign libresocsim_ram_bus_adr = libresocsim_shared_adr; assign libresocsim_ram_bus_dat_w = libresocsim_shared_dat_w; @@ -3054,6 +3263,34 @@ assign libresocsim_libresoc_xics_ics_stb = libresocsim_shared_stb; assign libresocsim_libresoc_xics_ics_we = libresocsim_shared_we; assign libresocsim_libresoc_xics_ics_cti = libresocsim_shared_cti; assign libresocsim_libresoc_xics_ics_bte = libresocsim_shared_bte; +assign interface0_converted_interface_adr = libresocsim_shared_adr; +assign interface0_converted_interface_dat_w = libresocsim_shared_dat_w; +assign interface0_converted_interface_sel = libresocsim_shared_sel; +assign interface0_converted_interface_stb = libresocsim_shared_stb; +assign interface0_converted_interface_we = libresocsim_shared_we; +assign interface0_converted_interface_cti = libresocsim_shared_cti; +assign interface0_converted_interface_bte = libresocsim_shared_bte; +assign interface1_converted_interface_adr = libresocsim_shared_adr; +assign interface1_converted_interface_dat_w = libresocsim_shared_dat_w; +assign interface1_converted_interface_sel = libresocsim_shared_sel; +assign interface1_converted_interface_stb = libresocsim_shared_stb; +assign interface1_converted_interface_we = libresocsim_shared_we; +assign interface1_converted_interface_cti = libresocsim_shared_cti; +assign interface1_converted_interface_bte = libresocsim_shared_bte; +assign interface2_converted_interface_adr = libresocsim_shared_adr; +assign interface2_converted_interface_dat_w = libresocsim_shared_dat_w; +assign interface2_converted_interface_sel = libresocsim_shared_sel; +assign interface2_converted_interface_stb = libresocsim_shared_stb; +assign interface2_converted_interface_we = libresocsim_shared_we; +assign interface2_converted_interface_cti = libresocsim_shared_cti; +assign interface2_converted_interface_bte = libresocsim_shared_bte; +assign interface3_converted_interface_adr = libresocsim_shared_adr; +assign interface3_converted_interface_dat_w = libresocsim_shared_dat_w; +assign interface3_converted_interface_sel = libresocsim_shared_sel; +assign interface3_converted_interface_stb = libresocsim_shared_stb; +assign interface3_converted_interface_we = libresocsim_shared_we; +assign interface3_converted_interface_cti = libresocsim_shared_cti; +assign interface3_converted_interface_bte = libresocsim_shared_bte; assign wb_sdram_adr = libresocsim_shared_adr; assign wb_sdram_dat_w = libresocsim_shared_dat_w; assign wb_sdram_sel = libresocsim_shared_sel; @@ -3072,16 +3309,20 @@ assign libresocsim_ram_bus_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel assign ram_bus_ram_bus_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[1]); assign libresocsim_libresoc_xics_icp_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[2]); assign libresocsim_libresoc_xics_ics_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[3]); -assign wb_sdram_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[4]); -assign libresocsim_libresocsim_wishbone_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[5]); -assign libresocsim_shared_err = (((((libresocsim_ram_bus_err | ram_bus_ram_bus_err) | libresocsim_libresoc_xics_icp_err) | libresocsim_libresoc_xics_ics_err) | wb_sdram_err) | libresocsim_libresocsim_wishbone_err); +assign interface0_converted_interface_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[4]); +assign interface1_converted_interface_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[5]); +assign interface2_converted_interface_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[6]); +assign interface3_converted_interface_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[7]); +assign wb_sdram_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[8]); +assign libresocsim_libresocsim_wishbone_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[9]); +assign libresocsim_shared_err = (((((((((libresocsim_ram_bus_err | ram_bus_ram_bus_err) | libresocsim_libresoc_xics_icp_err) | libresocsim_libresoc_xics_ics_err) | interface0_converted_interface_err) | interface1_converted_interface_err) | interface2_converted_interface_err) | interface3_converted_interface_err) | wb_sdram_err) | libresocsim_libresocsim_wishbone_err); assign libresocsim_wait = ((libresocsim_shared_stb & libresocsim_shared_cyc) & (~libresocsim_shared_ack)); always @(*) begin libresocsim_shared_ack <= 1'd0; libresocsim_error <= 1'd0; libresocsim_shared_dat_r <= 32'd0; - libresocsim_shared_ack <= (((((libresocsim_ram_bus_ack | ram_bus_ram_bus_ack) | libresocsim_libresoc_xics_icp_ack) | libresocsim_libresoc_xics_ics_ack) | wb_sdram_ack) | libresocsim_libresocsim_wishbone_ack); - libresocsim_shared_dat_r <= (((((({32{libresocsim_slave_sel_r[0]}} & libresocsim_ram_bus_dat_r) | ({32{libresocsim_slave_sel_r[1]}} & ram_bus_ram_bus_dat_r)) | ({32{libresocsim_slave_sel_r[2]}} & libresocsim_libresoc_xics_icp_dat_r)) | ({32{libresocsim_slave_sel_r[3]}} & libresocsim_libresoc_xics_ics_dat_r)) | ({32{libresocsim_slave_sel_r[4]}} & wb_sdram_dat_r)) | ({32{libresocsim_slave_sel_r[5]}} & libresocsim_libresocsim_wishbone_dat_r)); + libresocsim_shared_ack <= (((((((((libresocsim_ram_bus_ack | ram_bus_ram_bus_ack) | libresocsim_libresoc_xics_icp_ack) | libresocsim_libresoc_xics_ics_ack) | interface0_converted_interface_ack) | interface1_converted_interface_ack) | interface2_converted_interface_ack) | interface3_converted_interface_ack) | wb_sdram_ack) | libresocsim_libresocsim_wishbone_ack); + libresocsim_shared_dat_r <= (((((((((({32{libresocsim_slave_sel_r[0]}} & libresocsim_ram_bus_dat_r) | ({32{libresocsim_slave_sel_r[1]}} & ram_bus_ram_bus_dat_r)) | ({32{libresocsim_slave_sel_r[2]}} & libresocsim_libresoc_xics_icp_dat_r)) | ({32{libresocsim_slave_sel_r[3]}} & libresocsim_libresoc_xics_ics_dat_r)) | ({32{libresocsim_slave_sel_r[4]}} & interface0_converted_interface_dat_r)) | ({32{libresocsim_slave_sel_r[5]}} & interface1_converted_interface_dat_r)) | ({32{libresocsim_slave_sel_r[6]}} & interface2_converted_interface_dat_r)) | ({32{libresocsim_slave_sel_r[7]}} & interface3_converted_interface_dat_r)) | ({32{libresocsim_slave_sel_r[8]}} & wb_sdram_dat_r)) | ({32{libresocsim_slave_sel_r[9]}} & libresocsim_libresocsim_wishbone_dat_r)); if (libresocsim_done) begin libresocsim_shared_dat_r <= 32'd4294967295; libresocsim_shared_ack <= 1'd1; @@ -5433,7 +5674,7 @@ always @(posedge sys_clk_1) begin subfragments_state <= 1'd0; libresocsim_libresocsim_we <= 1'd0; libresocsim_grant <= 2'd0; - libresocsim_slave_sel_r <= 6'd0; + libresocsim_slave_sel_r <= 10'd0; libresocsim_count <= 20'd1000000; libresocsim_state <= 2'd0; end @@ -5441,8 +5682,8 @@ always @(posedge sys_clk_1) begin regs1 <= regs0; end -reg [31:0] mem[0:127]; -reg [6:0] memadr; +reg [31:0] mem[0:31]; +reg [4:0] memadr; always @(posedge sys_clk_1) begin if (libresocsim_we[0]) mem[libresocsim_adr][7:0] <= libresocsim_dat_w[7:0]; @@ -5576,6 +5817,7 @@ test_issuer test_issuer( .TAP_bus__tdi(libresocsim_libresoc_jtag_tdi), .TAP_bus__tms(libresocsim_libresoc_jtag_tms), .clk(sys_clk_1), + .clk_sel_i(libresocsim_libresoc_clk_sel), .core_bigendian_i(1'd0), .dbus__ack(libresocsim_libresoc_dbus_ack), .dbus__bte(1'd0), @@ -5736,6 +5978,30 @@ test_issuer test_issuer( .sdr_dq_9__pad__i(sdram_dq_i[9]), .sdr_ras_n__core__o(libresocsim_libresoc_constraintmanager_sdram_ras_n), .sdr_we_n__core__o(libresocsim_libresoc_constraintmanager_sdram_we_n), + .sram4k_0_wb__adr(libresocsim_libresoc_interface0_adr), + .sram4k_0_wb__cyc(libresocsim_libresoc_interface0_cyc), + .sram4k_0_wb__dat_w(libresocsim_libresoc_interface0_dat_w), + .sram4k_0_wb__sel(libresocsim_libresoc_interface0_sel), + .sram4k_0_wb__stb(libresocsim_libresoc_interface0_stb), + .sram4k_0_wb__we(libresocsim_libresoc_interface0_we), + .sram4k_1_wb__adr(libresocsim_libresoc_interface1_adr), + .sram4k_1_wb__cyc(libresocsim_libresoc_interface1_cyc), + .sram4k_1_wb__dat_w(libresocsim_libresoc_interface1_dat_w), + .sram4k_1_wb__sel(libresocsim_libresoc_interface1_sel), + .sram4k_1_wb__stb(libresocsim_libresoc_interface1_stb), + .sram4k_1_wb__we(libresocsim_libresoc_interface1_we), + .sram4k_2_wb__adr(libresocsim_libresoc_interface2_adr), + .sram4k_2_wb__cyc(libresocsim_libresoc_interface2_cyc), + .sram4k_2_wb__dat_w(libresocsim_libresoc_interface2_dat_w), + .sram4k_2_wb__sel(libresocsim_libresoc_interface2_sel), + .sram4k_2_wb__stb(libresocsim_libresoc_interface2_stb), + .sram4k_2_wb__we(libresocsim_libresoc_interface2_we), + .sram4k_3_wb__adr(libresocsim_libresoc_interface3_adr), + .sram4k_3_wb__cyc(libresocsim_libresoc_interface3_cyc), + .sram4k_3_wb__dat_w(libresocsim_libresoc_interface3_dat_w), + .sram4k_3_wb__sel(libresocsim_libresoc_interface3_sel), + .sram4k_3_wb__stb(libresocsim_libresoc_interface3_stb), + .sram4k_3_wb__we(libresocsim_libresoc_interface3_we), .TAP_bus__tdo(libresocsim_libresoc_jtag_tdo), .busy_o(libresocsim_libresoc1), .dbus__adr(libresocsim_libresoc_dbus_adr), @@ -5823,6 +6089,8 @@ test_issuer test_issuer( .mtwi_sda__pad__o(i2c_sda_o), .mtwi_sda__pad__oe(i2c_sda_oe), .pc_o(libresocsim_libresoc3), + .pll_18_o(libresocsim_libresoc_pll_18_o), + .pll_lck_o(libresocsim_libresoc_pll_lck_o), .sdr_a_0__pad__o(sdram_a[0]), .sdr_a_10__pad__o(sdram_a[10]), .sdr_a_11__pad__o(sdram_a[11]), @@ -5893,7 +6161,19 @@ test_issuer test_issuer( .sdr_dq_9__pad__o(sdram_dq_o[9]), .sdr_dq_9__pad__oe(sdram_dq_oe[9]), .sdr_ras_n__pad__o(sdram_ras_n), - .sdr_we_n__pad__o(sdram_we_n) + .sdr_we_n__pad__o(sdram_we_n), + .sram4k_0_wb__ack(libresocsim_libresoc_interface0_ack), + .sram4k_0_wb__dat_r(libresocsim_libresoc_interface0_dat_r), + .sram4k_0_wb__err(libresocsim_libresoc_interface0_err), + .sram4k_1_wb__ack(libresocsim_libresoc_interface1_ack), + .sram4k_1_wb__dat_r(libresocsim_libresoc_interface1_dat_r), + .sram4k_1_wb__err(libresocsim_libresoc_interface1_err), + .sram4k_2_wb__ack(libresocsim_libresoc_interface2_ack), + .sram4k_2_wb__dat_r(libresocsim_libresoc_interface2_dat_r), + .sram4k_2_wb__err(libresocsim_libresoc_interface2_err), + .sram4k_3_wb__ack(libresocsim_libresoc_interface3_ack), + .sram4k_3_wb__dat_r(libresocsim_libresoc_interface3_dat_r), + .sram4k_3_wb__err(libresocsim_libresoc_interface3_err) ); endmodule