From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Jul 2019 23:12:33 +0000 (-0700)
Subject: Fix box numbering
X-Git-Tag: working-ls180~881^2^2~282
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=73c8f1a59e69c5c2f06827d365afc6504fdfad82;p=yosys.git

Fix box numbering
---

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index a91720260..8bbdff6f4 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -23,7 +23,7 @@
 module \$__ABC_FF_ (input C, D, output Q);
 endmodule
 
-(* abc_box_id = 7, lib_whitebox, abc_flop = "FDRE,D,Q,\\$pastQ" *)
+(* abc_box_id = 8, lib_whitebox, abc_flop = "FDRE,D,Q,\\$pastQ" *)
 module \$__ABC_FDRE (output Q, input C, CE, D, R, \$pastQ );
   parameter [0:0] INIT = 1'b0;
   //parameter [0:0] IS_C_INVERTED = 1'b0;
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 69ff9aeab..1e1afbc1d 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -59,20 +59,20 @@ RAM128X1D 7 0 17 2
 
 # Inputs: C CE D R \$pastQ
 # Outputs: Q
-FDRE 7 1 5 1
+FDRE 8 1 5 1
 - 109 -46 358 0
 
 # Inputs: C CE D S \$pastQ
 # Outputs: Q
-FDSE 8 0 5 1
+FDSE 9 0 5 1
 - 109 -46 358 0
 
 # Inputs: C CE CLR D \$pastQ
 # Outputs: Q
-FDCE 9 0 5 1
+FDCE 10 0 5 1
 - 109 - -46 0
 
 # Inputs: C CE D PRE \$pastQ
 # Outputs: Q
-FDPE 10 0 5 1
+FDPE 11 0 5 1
 - 109 -46 - 0