From: clairexen <claire@symbioticeda.com>
Date: Fri, 2 Oct 2020 08:16:23 +0000 (+0200)
Subject: Merge pull request #2396 from YosysHQ/claire/empty-param
X-Git-Tag: working-ls180~251
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=73cd115e0866f2efea622ba5f54d39a621838baa;p=yosys.git

Merge pull request #2396 from YosysHQ/claire/empty-param

Ignore empty parameters in Verilog module instantiations
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73cd115e0866f2efea622ba5f54d39a621838baa