From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 19 Mar 2020 06:53:36 +0000 (+0000)
Subject: fix silly errors in power_fieldsn.py
X-Git-Tag: div_pipeline~1679
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=73d801a7740c1b197196c795df64586e6b27fd6b;p=soc.git

fix silly errors in power_fieldsn.py
---

diff --git a/src/soc/decoder/power_fieldsn.py b/src/soc/decoder/power_fieldsn.py
index 19d37102..819c40de 100644
--- a/src/soc/decoder/power_fieldsn.py
+++ b/src/soc/decoder/power_fieldsn.py
@@ -15,8 +15,7 @@ class SignalBitRange(BitRange):
 
     def __getitem__(self, subs):
         # *sigh* field numberings are bit-inverted.  PowerISA 3.0B section 1.3.2
-        print (dir(self))
-        print (self.items())
+        print ("SignalBitRange", subs, len(self), self.items())
         if isinstance(subs, slice):
             res = []
             print (subs)
@@ -28,9 +27,9 @@ class SignalBitRange(BitRange):
             if stop is None:
                 stop = -1
             if start < 0:
-                start = len(self) + start
+                start = len(self) + start + 1
             if stop < 0:
-                stop = len(self) + stop
+                stop = len(self) + stop + 1
             print ("range", start, stop, step)
             for t in range(start, stop, step):
                 t = len(self) - 1 - t # invert field back
@@ -40,7 +39,7 @@ class SignalBitRange(BitRange):
             return Cat(*res)
         else:
             if subs < 0:
-                subs = len(self) + sub
+                subs = len(self) + subs
             subs = len(self) - 1 - subs # invert field back
             k = OrderedDict.__getitem__(self, subs)
             return self.signal[self._rev(k)] # reverse-order here
diff --git a/src/soc/decoder/test/test_decoder_gas.py b/src/soc/decoder/test/test_decoder_gas.py
index 865192e9..d575f9b1 100644
--- a/src/soc/decoder/test/test_decoder_gas.py
+++ b/src/soc/decoder/test/test_decoder_gas.py
@@ -80,8 +80,9 @@ class DecoderTestCase(FHDLTestCase):
                 r3 = Register(random.randrange(32))
 
                 instruction_str = self.generate_opcode_string(opcode, r1, r2, r3)
-                print(instruction_str)
+                print("instr", instruction_str.strip())
                 instruction_bin = self.get_assembled_instruction(instruction_str)
+                print("code", hex(instruction_bin), bin(instruction_bin))
 
                 yield instruction.eq(instruction_bin)
                 yield Delay(1e-6)