From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 22 Jul 2022 22:45:49 +0000 (+0100)
Subject: table layout corrections
X-Git-Tag: opf_rfc_ls005_v1~1114
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=73d8a94ea2a9f21d9dd8941d9a97970ecff844a9;p=libreriscv.git

table layout corrections
---

diff --git a/openpower/sv/comparison_table.mdwn b/openpower/sv/comparison_table.mdwn
index 09ed6204e..c18ecff9b 100644
--- a/openpower/sv/comparison_table.mdwn
+++ b/openpower/sv/comparison_table.mdwn
@@ -1,6 +1,6 @@
 
-| ISA <br>name   | Num <br>opcodes | Taxonomy / <br> Class | Predicate <br> Masks | Twin <br> Predication |  Explicit <br> Vector regs | 128-bit | Bigint <br> capability | LDST <br> Fault-First | Data-dependent <br> Fail-first | Predicate-<br> Result | Matrix HW<br> support |
-|----------------|-----------------|-----------------------|----------------------|-----------------------|----------------------------|---------|------------------------|-----------------------|--------------------------------|-----------------------|-----------------------|
+| ISA <br>name   | Num <br>opcodes | Taxonomy / <br> Class | Predicate <br> Masks | Twin <br> Predication |  Explicit <br> Vector regs | 128-bit <br> operations | Bigint <br> capability | LDST <br> Fault-First | Data-dependent <br> Fail-first | Predicate-<br> Result | Matrix HW<br> support |
+|----------------|-----------------|-----------------------|----------------------|-----------------------|----------------------------|-------------------------|------------------------|-----------------------|--------------------------------|-----------------------|-----------------------|
 | SVP64          | 5 (1)           | Scalable (2)          | yes                  | yes (3)               | no (4)                     | see (5) | yes (6)                | yes (7)               | yes (8)                        | yes (9)               | yes (10)              |
 | VSX            | 700+            | Packed SIMD           | no                   | no                    | yes (11)                   | yes     | no                     | no                    | no                             | no                    | yes (12)              |
 | NEON           | ~250 (13)       | Predicated SIMD       | yes                  | no                    | yes                        | yes     | no                     | no                    | no                             | no                    | no                    |
@@ -32,5 +32,5 @@
 * (19): Like the original Cray RVV is a truly scalable Vector ISA (Cray setvl instruction).
 * (20): like SVP64 it is up to the hardware implementor to choose whether to support 128-bit elements.
 * (21): [NEC SX Aurora](https://ftp.libre-soc.org/NEC_SX_Aurora_TSUBASA_VectorEngine-as-manual-v1.2.pdf) is based on the original Cray Vectors
-* (22): [Aurora ISA guide)(https://sxauroratsubasa.sakura.ne.jp/documents/guide/pdfs/Aurora_ISA_guide.pdf) Appendix-3 11.1 p508
+* (22): [Aurora ISA guide](https://sxauroratsubasa.sakura.ne.jp/documents/guide/pdfs/Aurora_ISA_guide.pdf) Appendix-3 11.1 p508
 * (23): Like the original Cray Vectors, the ISA Vector Length is independent of the underlying hardware, however Generation 1 has 256 elements per Vector register (3.2.4 p24, Aurora ISA guide)