From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 12 May 2021 12:17:33 +0000 (+0100)
Subject: addcomments for MMU PortInterface test (how it, um, doesnt actually use PortInterface? :)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=73eead8350ad474b0a8e38b0f4a0b0d2cbb2a27e;p=soc.git

addcomments for MMU PortInterface test (how it, um, doesnt actually use PortInterface? :)
---

diff --git a/src/soc/experiment/test/test_mmu_dcache_pi.py b/src/soc/experiment/test/test_mmu_dcache_pi.py
index 46cc5571..ea342ba3 100644
--- a/src/soc/experiment/test/test_mmu_dcache_pi.py
+++ b/src/soc/experiment/test/test_mmu_dcache_pi.py
@@ -1,3 +1,9 @@
+"""MMU PortInterface Test
+
+quite basic, goes directly to the MMU to assert signals (does not
+yet use PortInterface)
+"""
+
 from nmigen import (C, Module, Signal, Elaboratable, Mux, Cat, Repl, Signal)
 from nmigen.cli import main
 from nmigen.cli import rtlil