From: Luke Kenneth Casson Leighton Date: Sun, 9 Dec 2018 01:31:35 +0000 (+0000) Subject: add conversation note X-Git-Tag: convert-csv-opcode-to-binary~4795 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=73fc49fa5abbc5e23e80ba22c945c5cd5a15c70d;p=libreriscv.git add conversation note --- diff --git a/3d_gpu/microarchitecture.mdwn b/3d_gpu/microarchitecture.mdwn index 4928444c6..bd20d476e 100644 --- a/3d_gpu/microarchitecture.mdwn +++ b/3d_gpu/microarchitecture.mdwn @@ -334,6 +334,24 @@ the size of the Reorder Buffer (preferably well below), and as long as it's guaranteed to be emptied by the time the ROB cycles through the whole buffer, it *should* be okay. +---- + +> Don't forget that in these days of Spectre and Meltdown, merely +> preventing dead instruction results from being written to registers or +> memory is NOT ENOUGH. You also need to prevent load instructions from +> altering cache and branch instructions from altering branch prediction +> state. + +Which, oddly enough, provides a necessity for being able to consume +multiple containers from the cache Miss buffers, which oddly enough, +are what makes a crucial mechanism in the Virtual Vector Method work. + +In the past, one would forward the demand container to the waiting +memref and then write the whole the line into the cache. S&M means you +have to forward multiple times from the miss buffers and avoid damaging +the cache until the instruction retires. VVM uses this to avoid having +a vector strip mine the data cache. + # References *