From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 25 Jun 2020 19:41:35 +0000 (+0100)
Subject: start connecting up Pi2LSUI
X-Git-Tag: div_pipeline~273
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7400c181c44d9db72b44772acbd85fa533375213;p=soc.git

start connecting up Pi2LSUI
---

diff --git a/src/soc/experiment/pi2ls.py b/src/soc/experiment/pi2ls.py
index 9be33016..97a42c86 100644
--- a/src/soc/experiment/pi2ls.py
+++ b/src/soc/experiment/pi2ls.py
@@ -10,7 +10,7 @@
 
     busy_o/1        most likely to be x_busy_o
     go_die_i/1      rst?
-    addr.data/48    x_addr_i[4:] (x_addr_i[:4] goes into LenExpand)
+    addr.data/48    x_addr_i (x_addr_i[:4] goes into LenExpand)
     addr.ok/1       probably x_valid_i & ~x_stall_i
 
     addr_ok_o/1     no equivalent.  *might* work using x_stall_i
@@ -32,11 +32,37 @@ from nmigen import Elaboratable, Module, Signal
 class Pi2LSUI(Elaboratable):
 
     def __init__(self, name, regwid=64, addrwid=48):
+        self.addrbits = 4
         self.pi = PortInterface(name="%s_pi", regwid, addrwid)
-        self.lsui = LoadStoreUnitInterface(addrwid, 4, regwid)
+        self.lsui = LoadStoreUnitInterface(addrwid, self.addrbits, regwid)
+
+    def splitaddr(self, addr):
+        """split the address into top and bottom bits of the memory granularity
+        """
+        return addr[:self.addrbits], addr[self.addrbits:]
 
     def elaborate(self, platform):
         m = Module()
-        m.submodules.lenexp = lenexp = LenExpand(4, 8)
+        pi, lsui, addrbits = self.pi, self.lsui, self.addrbits
+        m.submodules.lenexp = lenexp = LenExpand(self.addrbits, 8)
+
+        m.d.comb += lsui.x_ld_i.eq(pi.is_ld_i)
+        m.d.comb += lsui.x_st_i.eq(pi.is_st_i)
+
+        with m.If(pi.addr.ok):
+            # expand the LSBs of address plus LD/ST len into 16-bit mask
+            m.d.comb += lenexp.len_i.eq(pi.data_len)
+            m.d.comb += lenexp.addr_i.eq(pi.addr.data[addrbits]) # LSBs of addr
+            m.d.comb += lsui.x_mask_i.eq(lenexp.lexp_o)
+            # pass through the address, indicate "valid"
+            m.d.comb += lsui.x_addr_i.eq(pi.addr.data) # full address
+            m.d.comb += lsui.x_valid_i.eq(1)
+
+        with m.If(pi.is_ld_i):
+            m.d.comb += pi.ld.data.eq(lsui.m_ld_data_o)
+            #m.d.comb += pi.ld.ok.eq(TODO)
+
+        with m.If(pi.is_st_i & pi.st.ok):
+            m.d.comb += lsui.x_st_data_i.eq(pi.st.data)
 
         return m