From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 3 Nov 2020 14:11:28 +0000 (+0000)
Subject: add stlinkv2 photos
X-Git-Tag: convert-csv-opcode-to-binary~1880
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7414931d70ac72c5267acf32f49bd2a98c823535;p=libreriscv.git

add stlinkv2 photos
---

diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn
index 0dcff636e..65d430122 100644
--- a/HDL_workflow/ECP5_FPGA.mdwn
+++ b/HDL_workflow/ECP5_FPGA.mdwn
@@ -163,6 +163,12 @@ Luke do the labels of PCLK[C|T]0_[0|1] and GR_PCLK0_[0|1] have any significance?
 
 Additionally, does the note in the schematic about needing to swap EVEN and ODD pin numbers if using MALE VERTICAL header instead of FEMALE 90° ANGLED header apply to us?
 
+# STLinkV2 connector
+
+[[!img 2020-11-03_14-08.png size="900x" ]] 
+
+[[!img 2020-11-03_14-09.png size="900x" ]] 
+
 # VERSA ECP5 Connections
 
 Table of connections: