From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 25 Mar 2019 17:45:53 +0000 (+0000)
Subject: small tidyup of priority-encoding pipe mux
X-Git-Tag: ls180-24jan2020~1492
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=741ac2472ac70a10f9d485d1732dac312e1f0e60;p=ieee754fpu.git

small tidyup of priority-encoding pipe mux
---

diff --git a/src/add/example_buf_pipe.py b/src/add/example_buf_pipe.py
index cecb50d6..00955697 100644
--- a/src/add/example_buf_pipe.py
+++ b/src/add/example_buf_pipe.py
@@ -566,7 +566,7 @@ class UnbufferedPipeline(PipelineBase):
         for i in range(p_len):
             r = self.stage.ispec() # input type
             r_data.append(r)
-            data_valid.append(Signal(name="data_valid"))
+            data_valid.append(Signal(name="data_valid", reset_less=True))
             p_i_valid.append(Signal(name="p_i_valid", reset_less=True))
             n_i_readyn.append(Signal(name="n_i_readyn", reset_less=True))
             if hasattr(self.stage, "setup"):
@@ -603,11 +603,18 @@ class UnbufferedPipeline(PipelineBase):
             m.d.sync += eq(o_mid, mid)
 
             for i in range(p_len):
-                with m.If(self.p[i].i_valid & self.p[i].o_ready):
+                vr = Signal(reset_less=True)
+                m.d.comb += vr.eq(self.p[i].i_valid & self.p[i].o_ready)
+                with m.If(vr):
                     m.d.sync += eq(r_data[i], self.p[i].i_data)
 
             m.d.comb += eq(self.n[ni].o_data,
                            self.stage.process(r_data[o_mid]))
+            #with m.Switch(o_mid):
+            #    for i in range(p_len):
+            #        with m.Case(i):
+            #            m.d.comb += eq(self.n[ni].o_data,
+            #               self.stage.process(r_data[i]))
         else:
             for i in range(p_len):
                 m.d.comb += p_i_valid[i].eq(self.p[i].i_valid_logic())
diff --git a/src/add/test_prioritymux_pipe.py b/src/add/test_prioritymux_pipe.py
index 10b5ec6a..7cc5b817 100644
--- a/src/add/test_prioritymux_pipe.py
+++ b/src/add/test_prioritymux_pipe.py
@@ -51,9 +51,9 @@ class PriorityUnbufferedPipeline(UnbufferedPipeline):
 
 class PassData:
     def __init__(self):
-        self.mid = Signal(2)
-        self.idx = Signal(6)
-        self.data = Signal(16)
+        self.mid = Signal(2, reset_less=True)
+        self.idx = Signal(6, reset_less=True)
+        self.data = Signal(16, reset_less=True)
 
     def eq(self, i):
         return [self.mid.eq(i.mid), self.idx.eq(i.idx), self.data.eq(i.data)]
@@ -170,7 +170,7 @@ class InputTest:
         self.dut = dut
         self.di = {}
         self.do = {}
-        self.tlen = 4
+        self.tlen = 10
         for mid in range(dut.num_rows):
             self.di[mid] = {}
             self.do[mid] = {}