From: Luke Kenneth Casson Leighton Date: Sun, 18 Apr 2021 19:01:43 +0000 (+0100) Subject: core_stopped_i unused: remove X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=741ca3a380ad620602d03cc1acdb4e1ed2aa9d3b;p=soc.git core_stopped_i unused: remove --- diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index 91e639a5..215bcaab 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -107,7 +107,6 @@ class NonProductionCore(Elaboratable): self.busy_o = Signal(name="corebusy_o", reset_less=True) # start/stop and terminated signalling - self.core_stopped_i = Signal(reset_less=True) self.core_terminate_o = Signal(reset=0) # indicates stopped # create per-FU instruction decoders (subsetted) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 9df03bb0..eff31330 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -562,7 +562,6 @@ class TestIssuerInternal(Elaboratable): m.next = "INSN_WAIT" with m.Else(): # tell core it's stopped, and acknowledge debug handshake - comb += core.core_stopped_i.eq(1) comb += dbg.core_stopped_i.eq(1) # while stopped, allow updating the PC and SVSTATE with m.If(self.pc_i.ok): @@ -737,7 +736,6 @@ class TestIssuerInternal(Elaboratable): m.next = "PRED_SKIP" with m.Else(): - comb += core.core_stopped_i.eq(1) comb += dbg.core_stopped_i.eq(1) # while stopped, allow updating the PC and SVSTATE with m.If(self.pc_i.ok):