From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 19 Feb 2015 10:41:54 +0000 (+0100)
Subject: la: fix intput_buffer clocking when clk_domain is not "sys"
X-Git-Tag: 24jan2021_ls180~2575^2~10
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=741ecca5b4a06e296786ea7f50c75cef887a4d43;p=litex.git

la: fix intput_buffer clocking when clk_domain is not "sys"
---

diff --git a/litescope/frontend/la.py b/litescope/frontend/la.py
index 696a4ea4..cbe7dbc4 100644
--- a/litescope/frontend/la.py
+++ b/litescope/frontend/la.py
@@ -34,9 +34,13 @@ class LiteScopeLA(Module, AutoCSR):
 		sink = self.sink
 		# insert Buffer on sink (optional, can be used to improve timings)
 		if self.with_input_buffer:
-			self.submodules.buffer = Buffer(self.sink.description)
-			self.comb += Record.connect(sink, self.buffer.d)
-			sink = self.buffer.q
+			input_buffer = Buffer(self.sink.description)
+			if self.clk_domain is not "sys":
+				self.submodules += RenameClockDomains(input_buffer, clk_domain)
+			else:
+				self.submodules += input_buffer
+			self.comb += Record.connect(sink, intput_buffer.d)
+			sink = intput_buffer.q
 
 		# clock domain crossing (optional, required when capture_clk is not sys_clk)
 		# XXX : sys_clk must be faster than capture_clk, add Converter on data to remove this limitation