From: lkcl <lkcl@web>
Date: Mon, 3 Oct 2022 20:36:39 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~214
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=74289842b1613750fc9ae6b7ebee0b18015604e0;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls002.mdwn b/openpower/sv/rfc/ls002.mdwn
index 1288cface..3dd29fe79 100644
--- a/openpower/sv/rfc/ls002.mdwn
+++ b/openpower/sv/rfc/ls002.mdwn
@@ -12,17 +12,21 @@
 
 **Books and Section affected**:
 
+```
     Book I Scalar Floating-Point 4.6.2.1
     Appendix D Power ISA sorted by opcode
     Appendix E Power ISA sorted by version
     Appendix F Power ISA sorted by mnemonic
+```
 
 **Summary**
 
+```
     Instructions added
     fmvis - Floating-Point Move Immediate, Single
     fishmv - Floating-Point Immediate, Second-half Move
     (Potentially 64-bit prefixed of the same)
+```
 
 **Submitter**: Luke Leighton (Libre-SOC)
 
@@ -30,17 +34,23 @@
 
 **Impact on processor**:
 
+```
     Addition of two new FPR-based instructions
     (potentially 4 if EXT001 Prefixed variants added)
+```
 
 **Impact on software**:
 
+```
     Requires support for new instructions in assembler, debuggers,
     and related tools.
+```
 
 **Keywords**:
 
+```
     FPR, Floating-point, Load-immediate, BF16, FP32
+```
 
 **Motivation**