From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 5 May 2021 13:02:43 +0000 (+0100)
Subject: add saturate SVP64 RM mode decode
X-Git-Tag: 0.0.3~79
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=743160d70c1f8f59102bbf90f9548890eab85149;p=openpower-isa.git

add saturate SVP64 RM mode decode
---

diff --git a/src/openpower/decoder/power_svp64_rm.py b/src/openpower/decoder/power_svp64_rm.py
index 963f2cfb..981e51a8 100644
--- a/src/openpower/decoder/power_svp64_rm.py
+++ b/src/openpower/decoder/power_svp64_rm.py
@@ -142,6 +142,16 @@ class SVP64RMModeDecode(Elaboratable):
                     comb += self.pred_sz.eq(mode[SVP64MODE.SZ])
                     comb += self.pred_dz.eq(mode[SVP64MODE.DZ])
 
+        # extract saturate
+        with m.Switch(mode2):
+            with m.Case(2):
+                with m.If(mode[SVP64MODE.N]):
+                    comb += self.saturate.eq(SVP64sat.UNSIGNED)
+                with m.Else():
+                    comb += self.saturate.eq(SVP64sat.SIGNED)
+            with m.Default():
+                comb += self.saturate.eq(SVP64sat.NONE)
+
         # extract src/dest predicate.  use EXTRA3.MASK because EXTRA2.MASK
         # is in exactly the same bits
         srcmask = sel(m, self.rm_in.extra, EXTRA3.MASK)