From: Jean-Paul Chaput Date: Sun, 25 Oct 2020 20:39:29 +0000 (+0100) Subject: Experiment10 switched to the new chip2core module. X-Git-Tag: partial-core-ls180-gdsii~34 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7432d05ff698cbbee4cda4c3376bdf212400ee71;p=soclayout.git Experiment10 switched to the new chip2core module. --- diff --git a/experiments10/Makefile b/experiments10/Makefile index 2343504..e9b85e0 100755 --- a/experiments10/Makefile +++ b/experiments10/Makefile @@ -4,7 +4,7 @@ PHYSICAL_SYNTHESIS = Coriolis DESIGN_KIT = sxlib -# YOSYS_FLATTEN = Yes + YOSYS_FLATTEN = No CHIP = chip CORE = add MARGIN = 2 @@ -15,29 +15,33 @@ USE_CLOCKTREE = Yes USE_DEBUG = No USE_KITE = No -# RM_CHIP = Yes + RM_CHIP = Yes - NETLISTS = $(shell cat nets.txt) + NETLISTS = $(shell cat netlists.txt) # PATTERNS = add_r include ./mk/design-flow.mk +chip_r.vst: add.vst + -$(call scl_cols,$(call c2env, cgt -tV --script=doDesign)) + +chip_r.ap: chip_r.vst + blif: add.blif vst: add.vst -lvx: lvx-chip_cts_r -druc: druc-chip_cts_r -dreal: dreal-chip_cts_r -flatph: flatph-chip_cts_r -view: cgt-chip_cts_r - -layout: chip_cts_r.ap -gds: chip_cts_r.gds -gds_flat: chip_cts_r_flat.gds -cif: chip_cts_r.cif +lvx: lvx-chip_r +druc: druc-chip_r +dreal: dreal-chip_r +flatph: flatph-chip_r +view: cgt-chip_r +layout: chip_r.ap +gds: chip_r.gds +gds_flat: chip_r_flat.gds +cif: chip_r.cif -view: cgt-chip_cts_r -sim: asimut-add_cts_r +view: cgt-chip_r +sim: asimut-add_r diff --git a/experiments10/coriolis2/settings.py b/experiments10/coriolis2/settings.py index f93e33d..5a2d575 100644 --- a/experiments10/coriolis2/settings.py +++ b/experiments10/coriolis2/settings.py @@ -1,58 +1,36 @@ # -*- Mode:Python -*- +from __future__ import print_function import os import Cfg import CRL import Viewer #import node180.scn6m_deep_09 import symbolic.cmos -from helpers import l, u, n - - -Cfg.Configuration.pushDefaultPriority( Cfg.Parameter.Priority.UserFile ) - - -Viewer.Graphics.setStyle( 'Alliance.Classic [black]' ) - -Cfg.getParamBool ( 'misc.catchCore' ).setBool ( False ) -Cfg.getParamBool ( 'misc.info' ).setBool ( False ) -Cfg.getParamBool ( 'misc.paranoid' ).setBool ( False ) -Cfg.getParamBool ( 'misc.bug' ).setBool ( False ) -Cfg.getParamBool ( 'misc.logMode' ).setBool ( True ) -Cfg.getParamBool ( 'misc.verboseLevel1' ).setBool ( True ) -Cfg.getParamBool ( 'misc.verboseLevel2' ).setBool ( True ) -#Cfg.getParamInt ( 'misc.minTraceLevel' ).setInt ( 159 ) -#Cfg.getParamInt ( 'misc.maxTraceLevel' ).setInt ( 160 ) -Cfg.getParamEnumerate ( 'etesian.effort' ).setInt ( 2 ) -Cfg.getParamPercentage( 'etesian.spaceMargin' ).setPercentage( 20.0 ) -Cfg.getParamPercentage( 'etesian.aspectRatio' ).setPercentage( 100.0 ) -Cfg.getParamBool ( 'etesian.uniformDensity' ).setBool ( True ) -Cfg.getParamInt ( 'anabatic.edgeLenght' ).setInt ( 24 ) -Cfg.getParamInt ( 'anabatic.edgeWidth' ).setInt ( 8 ) -Cfg.getParamString ( 'anabatic.topRoutingLayer' ).setString ( 'METAL4') -Cfg.getParamInt ( 'katana.eventsLimit' ).setInt ( 1000000 ) -Cfg.getParamInt ( 'katana.hTracksReservedLocal' ).setInt ( 7 ) -Cfg.getParamInt ( 'katana.vTracksReservedLocal' ).setInt ( 6 ) -#Cfg.getParamInt ( 'clockTree.minimumSide' ).setInt ( l(1000) ) - -Cfg.Configuration.popDefaultPriority() - -#cellsTop = os.path.abspath( os.getcwd()+'/../cells' ) -if os.environ.has_key('CELLS_TOP'): - cellsTop = os.environ['CELLS_TOP'] -else: - cellsTop = '../../../cells' - -af = CRL.AllianceFramework.get() -env = af.getEnvironment() -env.addSYSTEM_LIBRARY( library=cellsTop+'/nsxlib', mode=CRL.Environment.Prepend ) -env.addSYSTEM_LIBRARY( library=cellsTop+'/mpxlib', mode=CRL.Environment.Prepend ) -#env.setCLOCK( '^clk$|m_clock' ) -env.setCLOCK( 'clk' ) -env.setPOWER( 'vdd' ) -env.setGROUND( 'vss' ) - -Cfg.Configuration.popDefaultPriority() - -print 'Successfully read user configuration' - +from helpers import overlay, l, u, n + +with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg: + cfg.misc.catchCore = False + cfg.misc.info = False + cfg.misc.paranoid = False + cfg.misc.bug = False + cfg.misc.logMode = True + cfg.misc.verboseLevel1 = True + cfg.misc.verboseLevel2 = True + cfg.etesian.graphics = 3 + cfg.etesian.spaceMargin = 0.05 + cfg.etesian.aspectRatio = 1.0 + cfg.anabatic.edgeLenght = 24 + cfg.anabatic.edgeWidth = 8 + cfg.anabatic.topRoutingLayer = 'METAL4' + cfg.katana.eventsLimit = 4000000 + cfg.etesian.effort = 2 + cfg.etesian.uniformDensity = True + cfg.katana.hTracksReservedLocal = 7 + cfg.katana.vTracksReservedLocal = 6 + Viewer.Graphics.setStyle( 'Alliance.Classic [black]' ) + af = CRL.AllianceFramework.get() + env = af.getEnvironment() + env.setCLOCK( '^clk|^ck' ) + +print( ' o Successfully run "<>/coriolis2/settings.py".' ) diff --git a/experiments10/doDesign.py b/experiments10/doDesign.py new file mode 100644 index 0000000..588b7dd --- /dev/null +++ b/experiments10/doDesign.py @@ -0,0 +1,84 @@ + +from __future__ import print_function +import sys +import traceback +import CRL +import helpers +from helpers.io import ErrorMessage +from helpers.io import WarningMessage +from helpers import trace +from helpers import l, u, n +import plugins +from Hurricane import DbU +from plugins.alpha.block.block import Block +from plugins.alpha.block.configuration import IoPin +from plugins.alpha.block.configuration import GaugeConf +from plugins.alpha.core2chip.cmos import CoreToChip +from plugins.alpha.chip.configuration import ChipConf +from plugins.alpha.chip.chip import Chip + + +af = CRL.AllianceFramework.get() + + +def scriptMain ( **kw ): + """The mandatory function to be called by Coriolis CGT/Unicorn.""" + global af + rvalue = True + try: + #helpers.setTraceLevel( 540 ) + usePadsPosition = True + buildChip = True + cell, editor = plugins.kwParseMain( **kw ) + cell = af.getCell( 'add', CRL.Catalog.State.Logical ) + if cell is None: + print( ErrorMessage( 2, 'doDesign.scriptMain(): Unable to load cell "{}".'.format('adder') )) + sys.exit( 1 ) + if editor: editor.setCell( cell ) + # Spec: | Side | Pos | Instance | Pad net |Core net | + ioPadsSpec = [ (IoPin.SOUTH, None, 'p_a0' , 'a(0)' , 'a(0)' ) + , (IoPin.SOUTH, None, 'p_a1' , 'a(1)' , 'a(1)' ) + , (IoPin.SOUTH, None, 'power_0' , 'vddpad' , 'vdd' ) + , (IoPin.SOUTH, None, 'p_a2' , 'a(2)' , 'a(2)' ) + , (IoPin.SOUTH, None, 'p_b3' , 'b(3)' , 'b(3)' ) + , (IoPin.EAST , None, 'clock_0' , 'clk' , 'clk' ) + , (IoPin.EAST , None, 'p_tms_0' , 'tms' , 'tms' ) + , (IoPin.EAST , None, 'p_tdo_0' , 'tdo' , 'tdo' ) + , (IoPin.EAST , None, 'p_tdi_0' , 'tdi' , 'tdi' ) + , (IoPin.EAST , None, 'p_b2' , 'b(2)' , 'b(2)' ) + , (IoPin.NORTH, None, 'p_b1' , 'b(1)' , 'b(1)' ) + , (IoPin.NORTH, None, 'ground_0' , 'vsspad' , 'vss' ) + , (IoPin.NORTH, None, 'p_b0' , 'b(0)' , 'b(0)' ) + , (IoPin.NORTH, None, 'rst' , 'rst' , 'rst' ) + , (IoPin.WEST , None, 'p_f3' , 'f(3)' , 'f(3)' ) + , (IoPin.WEST , None, 'p_f2' , 'f(2)' , 'f(2)' ) + , (IoPin.WEST , None, 'p_f1' , 'f(1)' , 'f(1)' ) + , (IoPin.WEST , None, 'p_f0' , 'f(0)' , 'f(0)' ) + , (IoPin.WEST , None, 'p_a3' , 'a(3)' , 'a(3)' ) + ] + adderConf = ChipConf( cell, ioPads=ioPadsSpec ) + adderConf.cfg.etesian.bloat = 'nsxlib' + adderConf.cfg.etesian.uniformDensity = True + adderConf.cfg.etesian.aspectRatio = 1.0 + adderConf.cfg.etesian.spaceMargin = 0.05 + adderConf.cfg.block.spareSide = l(350) + adderConf.editor = editor + adderConf.useSpares = True + adderConf.useClockTree = True + adderConf.bColumns = 2 + adderConf.bRows = 2 + adderConf.chipConf.name = 'chip' + adderConf.chipConf.ioPadGauge = 'pxlib' + adderConf.coreSize = ( l(1200), l(1200) ) + adderConf.chipSize = ( l(3200), l(3200) ) + adderToChip = CoreToChip( adderConf ) + adderToChip.buildChip() + chipBuilder = Chip( adderConf ) + rvalue = chipBuilder.doPnR() + chipBuilder.save() + except Exception, e: + helpers.io.catch( e ) + rvalue = False + sys.stdout.flush() + sys.stderr.flush() + return rvalue diff --git a/experiments10/netlists.txt b/experiments10/netlists.txt new file mode 100644 index 0000000..599bb5a --- /dev/null +++ b/experiments10/netlists.txt @@ -0,0 +1,5 @@ +add +fsm +idblock +irblock +jtag diff --git a/experiments10/nets.txt b/experiments10/nets.txt deleted file mode 100644 index 76d4bb8..0000000 --- a/experiments10/nets.txt +++ /dev/null @@ -1 +0,0 @@ -add