From: Mariusz Glebocki <mglebocki@antmicro.com>
Date: Mon, 1 Jun 2020 11:58:44 +0000 (+0200)
Subject: test/test_targets: add arty_symbiflow
X-Git-Tag: 24jan2021_ls180~245^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7434376c07e2a697f65c09e809bfadcf557e4ac6;p=litex.git

test/test_targets: add arty_symbiflow

Signed-off-by: Mariusz Glebocki <mglebocki@antmicro.com>
---

diff --git a/test/test_targets.py b/test/test_targets.py
index 055954f1..ec767b15 100644
--- a/test/test_targets.py
+++ b/test/test_targets.py
@@ -73,6 +73,13 @@ class TestTargets(unittest.TestCase):
         ])
         self.assertEqual(errors, 0)
 
+    def test_arty_symbiflow(self):
+        from litex.boards.targets.arty_symbiflow import BaseSoC
+        errors = build_test([
+            BaseSoC(**test_kwargs)
+        ])
+        self.assertEqual(errors, 0)
+
     # Kintex-7
     def test_genesys2(self):
         from litex.boards.targets.genesys2 import BaseSoC
@@ -112,21 +119,21 @@ class TestTargets(unittest.TestCase):
     def test_simple(self):
         platforms = []
         # Xilinx
-        platforms += ["minispartan6"]                              # Spartan6
-        platforms += ["arty", "netv2", "nexys4ddr", "nexys_video"] # Artix7
-        platforms += ["kc705", "genesys2"]                         # Kintex7
-        platforms += ["kcu105"]                                    # Kintex Ultrascale
+        platforms += ["minispartan6"]                                                # Spartan6
+        platforms += ["arty", "netv2", "nexys4ddr", "nexys_video", "arty_symbiflow"] # Artix7
+        platforms += ["kc705", "genesys2"]                                           # Kintex7
+        platforms += ["kcu105"]                                                      # Kintex Ultrascale
 
         # Altera/Intel
-        platforms += ["de0nano"]                                   # Cyclone4
+        platforms += ["de0nano"]                                                     # Cyclone4
 
         # Lattice
-        platforms += ["tinyfpga_bx"]                               # iCE40
-        platforms += ["machxo3"]                                   # MachXO3
-        platforms += ["versa_ecp5", "ulx3s"]                       # ECP5
+        platforms += ["tinyfpga_bx"]                                                 # iCE40
+        platforms += ["machxo3"]                                                     # MachXO3
+        platforms += ["versa_ecp5", "ulx3s"]                                         # ECP5
 
         # Microsemi
-        platforms += ["avalanche"]                                 # PolarFire
+        platforms += ["avalanche"]                                                   # PolarFire
 
         for p in platforms:
             with self.subTest(platform=p):