From: Cesar Strauss <cestrauss@gmail.com>
Date: Wed, 21 Apr 2021 17:06:07 +0000 (-0300)
Subject: Fix sense of "invert" signal
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=744a1a5af2fb9b128e4672dfb5b51e977aaea4f3;p=soc.git

Fix sense of "invert" signal

We want to put "1" in the mask, if the operation is to be performed.
The actual CR bits are: LT, GT, EQ and SO.
So, for those, we just copy the bit directly to the mask, as they are.
For GE, LE, NE and NS, we want to invert the bit first.
---

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index a5f7304f..66321857 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -124,28 +124,28 @@ def get_predcr(m, mask, name):
     with m.Switch(mask):
         with m.Case(SVP64PredCR.LT.value):
             comb += idx.eq(0)
-            comb += invert.eq(1)
+            comb += invert.eq(0)
         with m.Case(SVP64PredCR.GE.value):
             comb += idx.eq(0)
-            comb += invert.eq(0)
+            comb += invert.eq(1)
         with m.Case(SVP64PredCR.GT.value):
             comb += idx.eq(1)
-            comb += invert.eq(1)
+            comb += invert.eq(0)
         with m.Case(SVP64PredCR.LE.value):
             comb += idx.eq(1)
-            comb += invert.eq(0)
+            comb += invert.eq(1)
         with m.Case(SVP64PredCR.EQ.value):
             comb += idx.eq(2)
-            comb += invert.eq(1)
+            comb += invert.eq(0)
         with m.Case(SVP64PredCR.NE.value):
             comb += idx.eq(1)
-            comb += invert.eq(0)
+            comb += invert.eq(1)
         with m.Case(SVP64PredCR.SO.value):
             comb += idx.eq(3)
-            comb += invert.eq(1)
+            comb += invert.eq(0)
         with m.Case(SVP64PredCR.NS.value):
             comb += idx.eq(3)
-            comb += invert.eq(0)
+            comb += invert.eq(1)
     return idx, invert