From: Raptor Engineering Development Team <support@raptorengineering.com>
Date: Wed, 23 Feb 2022 01:18:43 +0000 (-0600)
Subject: Make Tercel register map a bit easier to read
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7451b09e78a2aa298339bef738634f43eb92a635;p=microwatt.git

Make Tercel register map a bit easier to read
---

diff --git a/README.tercel.md b/README.tercel.md
index 96a16d1..c767a1f 100644
--- a/README.tercel.md
+++ b/README.tercel.md
@@ -33,7 +33,7 @@ Core configuration:	0xc8050000
 
 # REGISTER MAP
 
-## [0x00 - 0x07) Device ID
+## [0x00 - 0x07] Device ID
 
  Device make/model unique identifier for PnP functionality
  Fixed value: 0x7c5250545350494d
@@ -48,15 +48,12 @@ Core configuration:	0xc8050000
  | 15:8  | Minor version |
  | 7:0   | Patch level   |
 
-## [0x0c - 0x0f)
-
- System clock frequency
+## [0x0c - 0x0f] System clock frequency
 
  Can be used to set divisor to meet specific SPI Flash clock frequency requirements
 
-## [0x10 - 0x13)
+## [0x10 - 0x13] PHY configuration register 1
 
- PHY configuration register 1
  Default: 0x00000a10
 
  | Bits  | Description                                                                                            |
@@ -87,9 +84,8 @@ Core configuration:	0xc8050000
  | 7                   | divide by 12                       |
  | ...                 | ...                                |
 
-## [0x14 - 0x17)
+## [0x14 - 0x17] Flash configuration register 1
 
- Flash configuration register 1
   Default: 0x13031303
 
  | Bits  | Description           |
@@ -99,9 +95,8 @@ Core configuration:	0xc8050000
  | 15:8  | SPI 4BA read command  |
  | 7:0   | SPI 3BA read command  |
 
-## [0x18 - 0x1b)
+## [0x18 - 0x1b] Flash configuration register 2
 
- Flash configuration register 2
   Default: 0xeceb0c0b
 
  | Bits  | Description                |
@@ -111,9 +106,8 @@ Core configuration:	0xc8050000
  | 15:8  | SPI 4BA fast read command  |
  | 7:0   | SPI 3BA fast read command  |
 
-## [0x1c - 0x1f)
+## [0x1c - 0x1f] Flash configuration register 3
 
- Flash configuration register 3
   Default: 0x34321202
 
  | Bits  | Description              |
@@ -123,18 +117,16 @@ Core configuration:	0xc8050000
  | 15:8  | SPI 4BA program command  |
  | 7:0   | SPI 3BA program command  |
 
-## [0x20 - 0x23)
+## [0x20 - 0x23] Flash configuration register 4
 
- Flash configuration register 4
   Default: 0x00000000
 
   Cycles to keep CS asserted after operation completion.  Used to support high-throughput multi-cycle transfers with specific Flash devices.
 
   See also "Flash configuration register 5"
 
-## [0x24 - 0x27)
+## [0x24 - 0x27] Flash configuration register 5
 
- Flash configuration register 5
   Default: 0x00000000
 
  | Bits | Description             |
@@ -143,9 +135,8 @@ Core configuration:	0xc8050000
  | 1    | Allow multicycle writes |
  | 0    | Allow multicycle reads  |
 
-## [0x28 - 0x2b)
+## [0x28 - 0x2b] Core control register 1
 
- Core control register 1
   Default: 0x00000000
 
  | Bits | Description |                          |
@@ -155,9 +146,7 @@ Core configuration:	0xc8050000
 
  User command mode operates in conjunction with "Core data register 1" to support custom (non-data-I/O) SPI commands.
 
-## [0x2c - 0x2f)
-
- Core data register 1
+## [0x2c - 0x2f] Core data register 1
 
  Data transfer to/from SPI device in user command mode