From: lkcl <lkcl@web>
Date: Sun, 19 Sep 2021 10:53:25 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~63
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7455c0f497ca5be18242674cd03757139f6d857e;p=libreriscv.git

---

diff --git a/lkcl.mdwn b/lkcl.mdwn
index 8b0faada2..e2ed25875 100644
--- a/lkcl.mdwn
+++ b/lkcl.mdwn
@@ -15,8 +15,6 @@ move things along from one stage to the next
 
  - Project Management
  - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
- - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
- - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
  - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
  - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
  - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
@@ -33,7 +31,6 @@ move things along from one stage to the next
  - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
  - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
  - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
- - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
  - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
  - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
  - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
@@ -56,10 +53,6 @@ move things along from one stage to the next
  - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
  - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
    - EUR 200
- - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
- - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
- - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
- - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
  - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API 
  - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
    - donated
@@ -73,6 +66,14 @@ move things along from one stage to the next
  - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation 
 
 ## Completed but not yet submitted:
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
+
 
  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
    - EUR 150