From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 23 Oct 2015 18:29:04 +0000 (+0200)
Subject: cores/liteeth_mini: adapt all phys to new migen
X-Git-Tag: 24jan2021_ls180~2106^2~16
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7459419ab4a48e1721122abf0d0fd1f2e15f2146;p=litex.git

cores/liteeth_mini: adapt all phys to new migen
---

diff --git a/misoc/cores/liteeth_mini/phy/gmii.py b/misoc/cores/liteeth_mini/phy/gmii.py
index b08a421c..bb3fc0bb 100644
--- a/misoc/cores/liteeth_mini/phy/gmii.py
+++ b/misoc/cores/liteeth_mini/phy/gmii.py
@@ -92,11 +92,7 @@ class LiteEthPHYGMIICRG(Module, AutoCSR):
 class LiteEthPHYGMII(Module, AutoCSR):
     def __init__(self, clock_pads, pads, with_hw_init_reset=True):
         self.dw = 8
-        self.submodules.crg = LiteEthPHYGMIICRG(clock_pads,
-                                                pads,
-                                                with_hw_init_reset)
-        self.submodules.tx = RenameClockDomains(LiteEthPHYGMIITX(pads),
-                                                "eth_tx")
-        self.submodules.rx = RenameClockDomains(LiteEthPHYGMIIRX(pads),
-                                                "eth_rx")
+        self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset)
+        self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYGMIITX(pads))
+        self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYGMIIRX(pads))
         self.sink, self.source = self.tx.sink, self.rx.source
diff --git a/misoc/cores/liteeth_mini/phy/mii.py b/misoc/cores/liteeth_mini/phy/mii.py
index 6ac19553..c5bf5271 100644
--- a/misoc/cores/liteeth_mini/phy/mii.py
+++ b/misoc/cores/liteeth_mini/phy/mii.py
@@ -105,6 +105,6 @@ class LiteEthPHYMII(Module, AutoCSR):
     def __init__(self, clock_pads, pads, with_hw_init_reset=True):
         self.dw = 8
         self.submodules.crg = LiteEthPHYMIICRG(clock_pads, pads, with_hw_init_reset)
-        self.submodules.tx = RenameClockDomains(LiteEthPHYMIITX(pads), "eth_tx")
-        self.submodules.rx = RenameClockDomains(LiteEthPHYMIIRX(pads), "eth_rx")
+        self.submodules.tx =  ClockDomainsRenamer("eth_tx")(LiteEthPHYMIITX(pads))
+        self.submodules.rx = ClockDomainsRenamer("eth_tx")(LiteEthPHYMIIRX(pads))
         self.sink, self.source = self.tx.sink, self.rx.source
diff --git a/misoc/cores/liteeth_mini/phy/s6rgmii.py b/misoc/cores/liteeth_mini/phy/s6rgmii.py
index ccef3ac1..1f312ace 100644
--- a/misoc/cores/liteeth_mini/phy/s6rgmii.py
+++ b/misoc/cores/liteeth_mini/phy/s6rgmii.py
@@ -155,9 +155,7 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
 class LiteEthPHYRGMII(Module, AutoCSR):
     def __init__(self, clock_pads, pads, with_hw_init_reset=True):
         self.dw = 8
-        self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads,
-                                                 pads,
-                                                 with_hw_init_reset)
+        self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset)
         self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))
         self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads))
         self.sink, self.source = self.tx.sink, self.rx.source