From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 16 Oct 2016 18:37:02 +0000 (+0200)
Subject: Build fixes for VS 2015
X-Git-Tag: yosys-0.7~23
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=74702b04c2775b062aa89b8a4704cd9135d2b048;p=yosys.git

Build fixes for VS 2015
---

diff --git a/passes/techmap/attrmvcp.cc b/passes/techmap/attrmvcp.cc
index 50eaf61df..1537def00 100644
--- a/passes/techmap/attrmvcp.cc
+++ b/passes/techmap/attrmvcp.cc
@@ -93,6 +93,7 @@ struct AttrmvcpPass : public Pass {
 
 			for (auto cell : module->selected_cells())
 			for (auto &conn : cell->connections())
+			{
 				if (driven_mode) {
 					if (cell->input(conn.first))
 						for (auto bit : sigmap(conn.second))
@@ -102,6 +103,7 @@ struct AttrmvcpPass : public Pass {
 						for (auto bit : sigmap(conn.second))
 							net2cells[bit].insert(cell);
 				}
+			}
 
 			for (auto wire : module->selected_wires())
 			{
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 96b88eb42..6784f48c3 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -1170,8 +1170,9 @@ struct FlattenPass : public Pass {
 				worker.flatten_do_list.erase(mod->name);
 			}
 		} else {
-			for (auto mod : vector<Module*>(design->modules()))
+			for (auto mod : vector<Module*>(design->modules())) {
 				while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { }
+			}
 		}
 
 		log("No more expansions possible.\n");