From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 26 Jun 2022 08:46:32 +0000 (+0100)
Subject: svp64_matrix.py svremap reduce to 7 args from 8 (again)
X-Git-Tag: sv_maxu_works-initial~321
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=74810fd6867e426d638dc34a2f97e627b530b40e;p=openpower-isa.git

svp64_matrix.py svremap reduce to 7 args from 8 (again)
---

diff --git a/src/openpower/decoder/isa/test_caller_svp64_matrix.py b/src/openpower/decoder/isa/test_caller_svp64_matrix.py
index c15479db..130f9472 100644
--- a/src/openpower/decoder/isa/test_caller_svp64_matrix.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_matrix.py
@@ -93,13 +93,13 @@ class DecoderTestCase(FHDLTestCase):
 
     def test_sv_remap2(self):
         """>>> lst = ["svshape 5, 4, 3, 0, 0",
-                        "svremap 31, 1, 2, 3, 0, 0, 0, 0",
+                        "svremap 31, 1, 2, 3, 0, 0, 0",
                        "sv.fmadds 0.v, 8.v, 16.v, 0.v"
                         ]
                 REMAP fmadds FRT, FRA, FRC, FRB
         """
         lst = SVP64Asm(["svshape 4, 3, 3, 0, 0",
-                        "svremap 31, 1, 2, 3, 0, 0, 0, 0",
+                        "svremap 31, 1, 2, 3, 0, 0, 0",
                        "sv.fmadds 0.v, 16.v, 32.v, 0.v"
                         ])
         lst = list(lst)