From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Fri, 16 Nov 2012 18:38:57 +0000 (+0100)
Subject: examples/pytholite/basic: demonstrate conversion to Verilog
X-Git-Tag: 24jan2021_ls180~2099^2~787
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=748741b49ade77c8604f1e06a57b6585a58ccfee;p=litex.git

examples/pytholite/basic: demonstrate conversion to Verilog
---

diff --git a/examples/pytholite/basic.py b/examples/pytholite/basic.py
index fa8ba9ba..91688dc0 100644
--- a/examples/pytholite/basic.py
+++ b/examples/pytholite/basic.py
@@ -3,6 +3,7 @@ from migen.actorlib.sim import *
 from migen.pytholite.compiler import make_pytholite
 from migen.sim.generic import Simulator
 from migen.sim.icarus import Runner
+from migen.fhdl import verilog
 
 layout = [("r", BV(32))]
 
@@ -32,12 +33,15 @@ def run_sim(ng):
 	del sim
 
 def main():
+	print("Simulating native Python:")
+	ng_native = SimActor(number_gen(), ("result", Source, layout))
+	run_sim(ng_native)
+	
 	print("Simulating Pytholite:")
 	ng_pytholite = make_pytholite(number_gen, dataflow=[("result", Source, layout)])
 	run_sim(ng_pytholite)
 	
-	print("Simulating native Python:")
-	ng_native = SimActor(number_gen(), ("result", Source, layout))
-	run_sim(ng_native)
+	print("Converting Pytholite to Verilog:")
+	print(verilog.convert(ng_pytholite.get_fragment()))
 
 main()