From: lkcl Date: Sat, 19 Dec 2020 21:26:33 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~1160 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=748c296ce79c10a91034eeaa75c9100e0ee6ba07;p=libreriscv.git --- diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index ff535877a..25daa1814 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -235,14 +235,14 @@ that the spec is shifted up by one bit Mode is an augmentation of SV behaviour. Some of these alterations are element-based (saturation), others involve post-analysis (predicate result) and others are Vector-based (mapreduce, fail-on-first). -| 0-1 | 2 3 4 description | -| --- | ------------------ | -| 00 | M sz CRM reduce mode (M=1). | -| 01 | inv CR-bit Rc=1: ffirst CR sel | -| 01 | inv sz dz Rc=0: ffirst z/nonz | -| 10 | N sz dz sat mode: N=0/1 u/s | -| 11 | inv CR-bit Rc=1: pred-result CR sel | -| 11 | inv sz dz Rc=0: pred-result z/nonz | +| 0-1 | 2 | 3 4 | description | +| --- | --- |---------|-------------------------- | +| 00 | M | sz CRM | reduce mode (M=1). | +| 01 | inv | CR-bit | Rc=1: ffirst CR sel | +| 01 | inv | sz dz | Rc=0: ffirst z/nonz | +| 10 | N | sz dz | sat mode: N=0/1 u/s | +| 11 | inv | CR-bit | Rc=1: pred-result CR sel | +| 11 | inv | sz dz | Rc=0: pred-result z/nonz | Mode types: