From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Fri, 1 Apr 2016 05:51:22 +0000 (-0700)
Subject: Fixed incorrect port name in cells_map.v
X-Git-Tag: yosys-0.7~271^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7498ff8041cdd464521a6802055a9893a0c6cf61;p=yosys.git

Fixed incorrect port name in cells_map.v
---

diff --git a/techlibs/greenpak4/cells_map.v b/techlibs/greenpak4/cells_map.v
index e24d24973..ce517d94b 100644
--- a/techlibs/greenpak4/cells_map.v
+++ b/techlibs/greenpak4/cells_map.v
@@ -5,7 +5,7 @@ module GP_DFFS(input D, CLK, nSET, output reg Q);
 		.SRMODE(1'b1),
 	) _TECHMAP_REPLACE_ (
 		.D(D),
-		.CLK(C),
+		.CLK(CLK),
 		.nSR(nSET),
 		.Q(Q)
 	);
@@ -18,7 +18,7 @@ module GP_DFFR(input D, CLK, nRST, output reg Q);
 		.SRMODE(1'b0),
 	) _TECHMAP_REPLACE_ (
 		.D(D),
-		.CLK(C),
+		.CLK(CLK),
 		.nSR(nRST),
 		.Q(Q)
 	);