From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 6 Apr 2019 02:36:43 +0000 (+0100)
Subject: use simpler logic for s_o_ready and d_valid
X-Git-Tag: ls180-24jan2020~1326
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=749e768ad8539d047f3f50f6d0feaae06eb27874;p=ieee754fpu.git

use simpler logic for s_o_ready and d_valid
---

diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index 7196e1d6..0c198aa7 100644
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -528,18 +528,11 @@ class ControlBase:
         if not self.p.stage_ctl:
             return m
 
-        # when the pipeline (buffered or otherwise) says "ready",
-        # test the *stage* "ready".
-
-        with m.If(self.p._o_ready):
-            m.d.comb += self.p.s_o_ready.eq(self.stage.p_o_ready)
-        with m.Else():
-            m.d.comb += self.p.s_o_ready.eq(0)
-
-        with m.If(self.n.i_ready):
-            m.d.comb += self.n.d_valid.eq(self.stage.d_valid)
-        with m.Else():
-            m.d.comb += self.n.d_valid.eq(0)
+        # intercept the previous (outgoing) "ready", combine with stage ready
+        m.d.comb += self.p.s_o_ready.eq(self.p._o_ready & self.stage.p_o_ready)
+
+        # intercept the next (incoming) "ready" and combine it with data valid
+        m.d.comb += self.n.d_valid.eq(self.n.i_ready & self.stage.d_valid)
 
         return m