From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 10 Jul 2020 13:30:28 +0000 (+0100)
Subject: re-add rc/oe back into LDST input record
X-Git-Tag: div_pipeline~108
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=74b304b89a7132d72a5bc85cf009668c3b91c7ac;p=soc.git

re-add rc/oe back into LDST input record
this for later use with st*cx because it writes CR and OV (and SO)
---

diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py
index 7fcea29e..cffa0316 100644
--- a/src/soc/fu/compunits/test/test_compunit.py
+++ b/src/soc/fu/compunits/test/test_compunit.py
@@ -286,12 +286,17 @@ class TestRunner(FHDLTestCase):
                     if self.funit == Function.LDST:
                         yield from dump_sim_memory(self, l0, sim, code)
 
-                    yield from self.iodef.check_cu_outputs(res, pdecode2,
-                                                            sim, cu.alu, code)
 
                     # sigh.  hard-coded.  test memory
                     if self.funit == Function.LDST:
                         yield from check_sim_memory(self, l0, sim, code)
+                        yield from self.iodef.check_cu_outputs(res, pdecode2,
+                                                                sim, cu,
+                                                                code)
+                    else:
+                        yield from self.iodef.check_cu_outputs(res, pdecode2,
+                                                                sim, cu.alu,
+                                                                code)
 
 
         sim.add_sync_process(process)
diff --git a/src/soc/fu/compunits/test/test_ldst_compunit.py b/src/soc/fu/compunits/test/test_ldst_compunit.py
index 921a4d28..7cbf6d90 100644
--- a/src/soc/fu/compunits/test/test_ldst_compunit.py
+++ b/src/soc/fu/compunits/test/test_ldst_compunit.py
@@ -25,8 +25,8 @@ class LDSTTestRunner(TestRunner):
 
         print ("check cu outputs", code, res)
 
-        rc = yield dec2.e.rc.data
-        op = yield dec2.e.insn_type
+        rc = yield dec2.e.do.rc.data
+        op = yield dec2.e.do.insn_type
         cridx_ok = yield dec2.e.write_cr.ok
         cridx = yield dec2.e.write_cr.data
 
diff --git a/src/soc/fu/ldst/ldst_input_record.py b/src/soc/fu/ldst/ldst_input_record.py
index 58e8f100..244f6789 100644
--- a/src/soc/fu/ldst/ldst_input_record.py
+++ b/src/soc/fu/ldst/ldst_input_record.py
@@ -9,11 +9,15 @@ class CompLDSTOpSubset(Record):
     a copy of the relevant subset information from Decode2Execute1Type
     needed for LD/ST operations.  use with eq_from_execute1 (below) to
     grab subsets.
+
+    note: rc / oe is needed (later) for st*cx when it comes to setting OV/SO
     """
     def __init__(self, name=None):
         layout = (('insn_type', InternalOp),
                   ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
                   ('zero_a', 1),
+                  ('rc', Layout((("rc", 1), ("rc_ok", 1)))), # for later
+                  ('oe', Layout((("oe", 1), ("oe_ok", 1)))), # for later
                   ('is_32bit', 1),
                   ('is_signed', 1),
                   ('data_len', 4),
diff --git a/src/soc/fu/ldst/test/test_pipe_caller.py b/src/soc/fu/ldst/test/test_pipe_caller.py
index 247b0e06..5e41cbf3 100644
--- a/src/soc/fu/ldst/test/test_pipe_caller.py
+++ b/src/soc/fu/ldst/test/test_pipe_caller.py
@@ -41,7 +41,7 @@ def get_cu_inputs(dec2, sim):
         res['rc'] = sim.gpr(data3).value
 
     # XER.so
-    oe = yield dec2.e.oe.data[0] & dec2.e.oe.ok
+    oe = yield dec2.e.do.oe.data[0] & dec2.e.do.oe.ok
     if oe:
         so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
         res['xer_so'] = so