From: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Date: Wed, 11 Mar 2020 07:57:37 +0000 (+0100)
Subject: radv: tune primitive binning for small chips
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=74e7b442f21db806a296876b84a332d212cef77b;p=mesa.git

radv: tune primitive binning for small chips

Based on PAL and RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4144>
---

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index da83aa562bb..7f32e135c63 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3477,8 +3477,13 @@ radv_get_binning_settings(const struct radv_physical_device *pdev)
 {
 	struct radv_binning_settings settings;
 	if (pdev->rad_info.has_dedicated_vram) {
-		settings.context_states_per_bin = 1;
-		settings.persistent_states_per_bin = 1;
+		if (pdev->rad_info.num_render_backends > 4) {
+			settings.context_states_per_bin = 1;
+			settings.persistent_states_per_bin = 1;
+		} else {
+			settings.context_states_per_bin = 3;
+			settings.persistent_states_per_bin = 8;
+		}
 		settings.fpovs_per_batch = 63;
 	} else {
 		/* The context states are affected by the scissor bug. */