From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 4 Jun 2018 01:32:09 +0000 (+0100)
Subject: clarify
X-Git-Tag: convert-csv-opcode-to-binary~5299
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=74e8a78250ee4ecbc94fe0beef23477df10f94d7;p=libreriscv.git

clarify
---

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 5a148ebb5..69b05d302 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -82,7 +82,8 @@
 		 of pipeline setup, amount of state to context switch
 		 and software portability\vspace{4pt}
    \item How?
-	     By implicitly marking INT/FP regs as "Vectorised",\\
+	     By marking INT/FP regs as "Vectorised" and
+	     adding a level of indirection,
 	     SV expresses how existing instructions should act 
 	     on [contiguous] blocks of registers, in parallel.\vspace{4pt}
    \item What?
@@ -133,7 +134,8 @@
 \frame{\frametitle{How is Parallelism abstracted in Simple-V?}
 
  \begin{itemize}
-   \item Register "typing" turns any op into an implicit Vector op\vspace{10pt}
+   \item Register "typing" turns any op into an implicit Vector op:\\
+         registers are reinterpreted through a level of indirection
    \item Primarily at the Instruction issue phase (except SIMD)\\
          Note: it's ok to pass predication through to ALU (like SIMD)
    \item Standard (and future, and custom) opcodes now parallel\vspace{10pt}