From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 4 Oct 2019 23:46:15 +0000 (-0700)
Subject: Fix xilinx_dsp for unsigned extensions
X-Git-Tag: working-ls180~1010
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=74ef8feeaf63b41e8948ce09d40420ccdb48957a;p=yosys.git

Fix xilinx_dsp for unsigned extensions
---

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 3d0b1f2c3..4e174e753 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -277,7 +277,9 @@ match postAdd
 	index <SigBit> port(postAdd, AB)[0] === sigP[0]
 	filter GetSize(port(postAdd, AB)) >= GetSize(sigP)
 	filter port(postAdd, AB).extract(0, GetSize(sigP)) == sigP
-	filter port(postAdd, AB).extract_end(GetSize(sigP)) == SigSpec(sigP[GetSize(sigP)-1], GetSize(port(postAdd, AB))-GetSize(sigP))
+	// Check that remainder of AB is a sign-extension
+	define <bool> AB_SIGNED (param(postAdd, AB == \A ? \A_SIGNED : \B_SIGNED).as_bool())
+	filter port(postAdd, AB).extract_end(GetSize(sigP)) == SigSpec(AB_SIGNED ? sigP[GetSize(sigP)-1] : State::S0, GetSize(port(postAdd, AB))-GetSize(sigP))
 	set postAddAB AB
 	optional
 endmatch