From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 29 May 2019 09:41:25 +0000 (+0100)
Subject: latch opcode on instruction issue
X-Git-Tag: div_pipeline~1935
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=74f0f29c99d60a7ed805f949ca7ca94b1e3028ee;p=soc.git

latch opcode on instruction issue
---

diff --git a/src/experiment/compalu.py b/src/experiment/compalu.py
index 446c7e0f..f517f5cc 100644
--- a/src/experiment/compalu.py
+++ b/src/experiment/compalu.py
@@ -122,7 +122,7 @@ class ComputationUnitNoDelay(Elaboratable):
         #    m.d.comb += self.alu.op.eq(self.oper_i)
 
         # create a latch/register for the operand
-        latchregister(m, self.oper_i, self.alu.op, opc_l.qn)
+        latchregister(m, self.oper_i, self.alu.op, self.issue_i)
 
         # and one for the output from the ALU
         data_r = Signal(self.rwid, reset_less=True) # Dest register