From: lkcl <lkcl@web>
Date: Mon, 4 Oct 2021 03:34:46 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~3722
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=75091d7d4fc8cd6dbf56d8a8094da6aefab3aa0b;p=libreriscv.git

---

diff --git a/3d_gpu/architecture/dynamic_simd.mdwn b/3d_gpu/architecture/dynamic_simd.mdwn
index f333f5911..88b39b8da 100644
--- a/3d_gpu/architecture/dynamic_simd.mdwn
+++ b/3d_gpu/architecture/dynamic_simd.mdwn
@@ -19,7 +19,7 @@ of nmigen language constructs:
 * Type 2 high-level DSL. Implemented as Module in nmigen.hdl.dsl
 
 The Type 1 AST low-level proposed modifications mirror and extend the
-existing long-established python `operator` module, which nmigen
+existing long-established python `operator` module interoperability, which nmigen
 *already leverages* by providing `Value.__add__` and other operator
 overrides.