From: Luke Kenneth Casson Leighton Date: Thu, 22 Mar 2018 09:35:35 +0000 (+0000) Subject: add interface reader X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=750d9f1fd0a53acb208692814443b7518978b1b0;p=pinmux.git add interface reader --- diff --git a/interfaces.txt b/interfaces.txt new file mode 100644 index 0000000..5a1a4e2 --- /dev/null +++ b/interfaces.txt @@ -0,0 +1,6 @@ +uart 4 +spi 1 +twi 2 +sd 2 +jtag 2 +pwm 1 diff --git a/jtag.txt b/jtag.txt new file mode 100644 index 0000000..494fbd2 --- /dev/null +++ b/jtag.txt @@ -0,0 +1,5 @@ +tdi in +tms in +tclk in +trst in +tdo out diff --git a/pwm.txt b/pwm.txt new file mode 100644 index 0000000..76b0c8b --- /dev/null +++ b/pwm.txt @@ -0,0 +1 @@ +pwm out diff --git a/sd.txt b/sd.txt new file mode 100644 index 0000000..f06731c --- /dev/null +++ b/sd.txt @@ -0,0 +1,6 @@ +clk out +cmd out +d0 outen +d1 outen +d2 outen +d3 outen diff --git a/spi.txt b/spi.txt new file mode 100644 index 0000000..a7c9d79 --- /dev/null +++ b/spi.txt @@ -0,0 +1,4 @@ +sclk out +mosi out +nss out +miso in diff --git a/src/interface_decl.py b/src/interface_decl.py index bbdd22e..1e85581 100644 --- a/src/interface_decl.py +++ b/src/interface_decl.py @@ -1,3 +1,4 @@ +from UserDict import UserDict class Pin(object): """ pin interface declaration. @@ -166,6 +167,39 @@ class IOInterface(Interface): return "cell{0}_mux_in" +class Interfaces(UserDict): + """ contains a list of interface definitions + """ + + def __init__(self): + self.ifacecount = [] + ifaces = {} + with open('interfaces.txt', 'r') as ifile: + for l in ifile.readlines(): + l = l.strip() + l = l.split("\t") + print l + name = l[0] + count = int(l[1]) + self.ifacecount.append((name, count)) + spec = self.read_spec(name) + ifaces[name] = Interface(name, spec) + UserDict.__init__(self, ifaces) + + def read_spec(self, name): + spec = [] + with open('%s.txt' % name, 'r') as sfile: + for l in sfile.readlines(): + l = l.split("\t") + d = {'name': l[0]} + if l[1] == 'out': + d['action'] = True + elif l[1] == 'inout': + d['outen'] = True + spec.append(d) + return spec + + # ========= Interface declarations ================ # mux_interface = Interface('cell', [{'name': 'mux', 'ready':False, @@ -227,6 +261,8 @@ pwminterface_decl = Interface('pwm', [{'name': "pwm", 'action': True} ]) +ifaces = Interfaces() + # ======================================= # # basic test diff --git a/twi.txt b/twi.txt new file mode 100644 index 0000000..a673042 --- /dev/null +++ b/twi.txt @@ -0,0 +1,2 @@ +sda outen +scl outen diff --git a/uart.txt b/uart.txt new file mode 100644 index 0000000..9af527f --- /dev/null +++ b/uart.txt @@ -0,0 +1,2 @@ +rx in +tx out