From: Alberto Gonzalez <boqwxp@airmail.cc>
Date: Sat, 22 Feb 2020 06:29:11 +0000 (+0000)
Subject: Closes #1714. Fix make failure when NDEBUG=1.
X-Git-Tag: working-ls180~789^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=750e7a9a541676f64fc9def64e669f94fa074d28;p=yosys.git

Closes #1714. Fix make failure when NDEBUG=1.
---

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 8f5718411..54605f90e 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -752,13 +752,11 @@ void reintegrate(RTLIL::Module *module)
 				continue;
 			}
 
-#ifndef NDEBUG
 			RTLIL::Module* box_module = design->module(existing_cell->type);
 			IdString derived_type = box_module->derive(design, existing_cell->parameters);
 			RTLIL::Module* derived_module = design->module(derived_type);
 			log_assert(derived_module);
 			log_assert(mapped_cell->type == stringf("$__boxid%d", derived_module->attributes.at("\\abc9_box_id").as_int()));
-#endif
 			mapped_cell->type = existing_cell->type;
 
 			RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);