From: Marek Olšák Date: Wed, 20 Nov 2013 12:48:19 +0000 (+0100) Subject: radeonsi: implement MSAA for CIK X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=751e8697f2099a0ceaba09e0d8775e4636f209b1;p=mesa.git radeonsi: implement MSAA for CIK There are also some changes to the printfs. Reviewed-and-Tested-by: Michel Dänzer --- diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index 77b05c4a25e..5674f0b7e87 100644 --- a/src/gallium/drivers/radeon/r600_texture.c +++ b/src/gallium/drivers/radeon/r600_texture.c @@ -403,6 +403,10 @@ static void si_texture_get_cmask_info(struct r600_common_screen *rscreen, cl_width = 64; cl_height = 32; break; + case 16: /* Hawaii */ + cl_width = 64; + cl_height = 64; + break; default: assert(0); return; @@ -585,15 +589,15 @@ r600_texture_create_object(struct pipe_screen *screen, (rtex->resource.b.b.last_level > 0 && rscreen->debug_flags & DBG_TEXMIP)) { printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, " "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, " - "bpe=%u, nsamples=%u, flags=%u\n", + "bpe=%u, nsamples=%u, flags=0x%x, %s\n", rtex->surface.npix_x, rtex->surface.npix_y, rtex->surface.npix_z, rtex->surface.blk_w, rtex->surface.blk_h, rtex->surface.blk_d, rtex->surface.array_size, rtex->surface.last_level, rtex->surface.bpe, rtex->surface.nsamples, - rtex->surface.flags); + rtex->surface.flags, util_format_short_name(base->format)); for (int i = 0; i <= rtex->surface.last_level; i++) { - printf(" Z %i: offset=%llu, slice_size=%llu, npix_x=%u, " + printf(" L %i: offset=%llu, slice_size=%llu, npix_x=%u, " "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, " "nblk_z=%u, pitch_bytes=%u, mode=%u\n", i, rtex->surface.level[i].offset, diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.c b/src/gallium/drivers/radeonsi/radeonsi_pipe.c index 1f9279159dc..e662e7886b4 100644 --- a/src/gallium/drivers/radeonsi/radeonsi_pipe.c +++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.c @@ -333,7 +333,9 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) return 1; case PIPE_CAP_TEXTURE_MULTISAMPLE: - return HAVE_LLVM >= 0x0304 && rscreen->b.chip_class == SI; + /* 2D tiling on CIK is supported since DRM 2.35.0 */ + return HAVE_LLVM >= 0x0304 && (rscreen->b.chip_class < CIK || + rscreen->b.info.drm_minor >= 35); case PIPE_CAP_TGSI_TEXCOORD: return 0; diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 27428366cfe..fd5d2c699f1 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -1491,7 +1491,11 @@ boolean si_is_format_supported(struct pipe_screen *screen, return FALSE; if (sample_count > 1) { - if (HAVE_LLVM < 0x0304 || rscreen->b.chip_class != SI) + if (HAVE_LLVM < 0x0304) + return FALSE; + + /* 2D tiling on CIK is supported since DRM 2.35.0 */ + if (rscreen->b.chip_class >= CIK && rscreen->b.info.drm_minor < 35) return FALSE; switch (sample_count) { @@ -1567,7 +1571,7 @@ static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4, struct r600_surface *surf; unsigned level = state->cbufs[cb]->u.tex.level; unsigned pitch, slice; - unsigned color_info, color_attrib; + unsigned color_info, color_attrib, color_pitch; unsigned tile_mode_index; unsigned format, swap, ntype, endian; uint64_t offset; @@ -1655,6 +1659,8 @@ static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4, S_028C70_NUMBER_TYPE(ntype) | S_028C70_ENDIAN(endian); + color_pitch = S_028C64_TILE_MAX(pitch); + color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) | S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1); @@ -1668,9 +1674,15 @@ static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4, color_info |= S_028C70_COMPRESSION(1); unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height); - /* due to a bug in the hw, FMASK_BANK_HEIGHT must be set on SI too */ - color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index) | - S_028C74_FMASK_BANK_HEIGHT(fmask_bankh); + color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index); + + if (rctx->b.chip_class == SI) { + /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */ + color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh); + } + if (rctx->b.chip_class >= CIK) { + color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1); + } } } @@ -1681,10 +1693,9 @@ static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4, offset += r600_resource_va(rctx->b.b.screen, state->cbufs[cb]->texture); offset >>= 8; - /* FIXME handle enabling of CB beyond BASE8 which has different offset */ si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE); si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset); - si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, S_028C64_TILE_MAX(pitch)); + si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, color_pitch); si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice)); if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {