From: lkcl <lkcl@web>
Date: Thu, 7 Apr 2022 16:36:38 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2859
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=752187a5ffdab38174bea74d3b17284fb349a633;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 810ef644f..f386181c4 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -548,12 +548,12 @@ if ¬predicate_bit & ¬SVRMmode.sz then
     CTR = CTR - 1
   stop # instruction finishes here
 if ¬BO[2] & ¬(CTRtest & (cond_ok ^ CTi)) then CTR <- CTR - 1
-lr_ok <- SVRMmode.LRu
+lr_ok <- LK
 if ctr_ok & cond_ok then
   if AA then NIA <-iea EXTS(BD || 0b00)
   else       NIA <-iea CIA + EXTS(BD || 0b00)
-  lr_ok <- ¬lr_ok
-if (LK & lr_ok) | (¬LK & lr_ok) then LR <-iea CIA + 4
+  if SVRMmode.LRu then lr_ok <- ¬lr_ok
+if lr_ok then LR <-iea CIA + 4
 ```
 
 Below is the pseudocode for SVP64 Branches, which is a little less