From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 6 May 2019 18:57:15 +0000 (+0200)
Subject: Merge pull request #946 from YosysHQ/clifford/specify
X-Git-Tag: yosys-0.9~141
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=752553d8e91643228714e04d9887d32f5d47870a;p=yosys.git

Merge pull request #946 from YosysHQ/clifford/specify

Add specify parser
---

752553d8e91643228714e04d9887d32f5d47870a
diff --cc frontends/verilog/verilog_parser.y
index 46b3a9025,4914b2c18..d23009e60
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@@ -94,9 -94,23 +94,23 @@@ static void free_attr(std::map<std::str
  	delete al;
  }
  
+ struct specify_target {
+ 	char polarity_op;
+ 	AstNode *dst, *dat;
+ };
+ 
+ struct specify_triple {
+ 	AstNode *t_min, *t_avg, *t_max;
+ };
+ 
+ struct specify_rise_fall {
+ 	specify_triple rise;
+ 	specify_triple fall;
+ };
+ 
  %}
  
 -%name-prefix "frontend_verilog_yy"
 +%define api.prefix {frontend_verilog_yy}
  
  %union {
  	std::string *string;