From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 24 Oct 2022 09:54:53 +0000 (+0100)
Subject: add maxs. combined with cmp capability
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=753ba7273a910ba697173d58ea998f7730e6849d;p=openpower-isa.git

add maxs. combined with cmp capability
https://bugs.libre-soc.org/show_bug.cgi?id=915
---

diff --git a/openpower/isa/av.mdwn b/openpower/isa/av.mdwn
index 057135e4..9246b8f6 100644
--- a/openpower/isa/av.mdwn
+++ b/openpower/isa/av.mdwn
@@ -2,12 +2,32 @@
 <!-- https://libre-soc.org/openpower/sv/bitmanip/ -->
 <!-- https://libre-soc.org/openpower/sv/av_opcodes/ -->
 
+# DRAFT Fixed Point Signed Max (Rc=1)
+
+X-Form
+
+* maxs. RT,RA,RB (Rc=1)
+
+Pseudo-code:
+
+    a <- (RA)
+    b <- (RB)
+    if   a > b then RT <- a
+    else            RT <- b
+    if      a < b then c <-  0b100
+    else if a > b then c <-  0b010
+    else               c <-  0b001
+    CR0 <-  c || XER[SO]
+
+Special Registers Altered:
+
+    CR0                     (if Rc=1)
+
 # DRAFT Fixed Point Signed Max
 
 X-Form
 
 * maxs  RT,RA,RB (Rc=0)
-* maxs. RT,RA,RB (Rc=1)
 
 Pseudo-code:
 
@@ -16,7 +36,7 @@ Pseudo-code:
 
 Special Registers Altered:
 
-    CR0                     (if Rc=1)
+    None
 
 # DRAFT Fixed Point Unsigned Max
 
diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 92c76106..9b42862d 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1829,6 +1829,8 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
         # look up instruction in ISA.instrs, prepare namespace
         if ins_name == 'pcdec':  # grrrr yes there are others ("stbcx." etc.)
             info = self.instrs[ins_name+"."]
+        elif asmop[-1] == '.' and asmop in self.instrs:
+            info = self.instrs[asmop]
         else:
             info = self.instrs[ins_name]
         yield from self.prep_namespace(ins_name, info.form, info.op_fields,
diff --git a/src/openpower/test/bitmanip/av_cases.py b/src/openpower/test/bitmanip/av_cases.py
index 8468dad0..e4a06f2d 100644
--- a/src/openpower/test/bitmanip/av_cases.py
+++ b/src/openpower/test/bitmanip/av_cases.py
@@ -64,7 +64,7 @@ class AVTestCase(TestAccumulatorBase):
         e.intregs[1] = 0xc523e996a8ff6215
         e.intregs[2] = 0
         e.intregs[3] = 0
-        e.crregs[0] = 0x2 # RT is zero
+        e.crregs[0] = 0x8 # RB greater (arithmeticslly)
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
     def case_4_maxs_(self):
@@ -97,6 +97,20 @@ class AVTestCase(TestAccumulatorBase):
         e.crregs[0] = 0x4 # RT is +ve
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
+    def case_6_maxs_(self):
+        lst = [f"maxs. 3, 1, 2"]
+        lst = list(SVP64Asm(lst, bigendian))
+
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x8000_0000_0000_0000
+        initial_regs[2] = 0x8000_0000_0000_0000
+        e = ExpectedState(pc=4)
+        e.intregs[1] = 0x8000_0000_0000_0000
+        e.intregs[2] = 0x8000_0000_0000_0000
+        e.intregs[3] = 0x8000_0000_0000_0000
+        e.crregs[0] = 0x2 # values are equal
+        self.add_case(Program(lst, bigendian), initial_regs, expected=e)
+
     def case_0_mins(self):
         lst = ["mins 3, 1, 2"]
         lst = list(SVP64Asm(lst, bigendian))